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參數(shù)資料
| 型號： | TDA6170X |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 接收器 |
| 英文描述： | FM, AUDIO DEMODULATOR, PDSO28 |
| 封裝： | PLASTIC, DSO-28 |
| 文件頁數(shù)： | 16/27頁 |
| 文件大?。?/td> | 416K |
| 代理商： | TDA6170X |
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Data Sheet
TDA6170X
Semiconductor Group
19
21.7.99
total harmonic distortion
THD
0.2
0.5
%
VMIXIN > 2 mV
f = 27kHz,
fmod = 1kHz,
Control Byte = 000
0.2
0.5
%
VMIXIN > 2 mV
f = 50kHz,
fmod = 1kHz,
Control Byte = 011
signal to noise ratio
S/N
70
75
dB
A-weighted,
f = 27kHz,
fmod = 1kHz,
Control Byte = 000
Mute attenuation
aMUTE
75
90
dB
Control Byte = 111
I2C-Bus Interface
LOW level input voltage for both
SDA and SCL
VIL
-0.5
1.5
V
HIGH level input voltage for both
SDA and SCL
VIH
3
VVD +
0.5
V
Hysteresis of Schmitt trigger
inputs
Vhys
0.2
V
Pulse width of spikes which must
be suppressed by the input lters
tSP
50
ns
LOW level output voltage (open
collector)
VOL1
VOL2
0
0.4
0.6
V
3 mA sink current
6 mA sink current
Output fall time from
VIHmin to VILmax with a bus
capacitance from 10 pF to 400 pF
tOF
20 +
0.1Cb
250
ns
Input current for both SDA + SCL
Ii
-10
10
A
SCL clock frequency
fSCL
0
400
kHz
Bus free time between a STOP
and START condition
tBUF
1.3
s
Hold time (repeated) START con-
dition. After this period, the rst
clock pulse is generated
tHD,STA
0.6
s
LOW period of the SCL clock
tLOW
1.3
s
HIGH period of the SCL clock
tHIGH
0.6
s
Set-up time for repeated START
condition
tSU,DAT
0.6
s
Data hold time:
for I2C-bus devices
tHD,DAT
0
0.9
s
Data set-up time
tSU,DAT
100
ns
Rise time of both SDA + SCL
tR
20 +
0.1Cb
300
ns
Parameter
Symbol
Limit Values
Unit
Test conditions
min
typ
max
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