- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄98192 > TDA6060G (INFINEON TECHNOLOGIES AG) SPECIALTY CONSUMER CIRCUIT, PDSO28 PDF資料下載
參數(shù)資料
| 型號(hào)： | TDA6060G |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO28 |
| 封裝： | PLASTIC, TSSOP-28 |
| 文件頁(yè)數(shù)： | 24/27頁(yè) |
| 文件大?。?/td> | 421K |
| 代理商： | TDA6060G |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)當(dāng)前第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)
SIEMENS
Preliminary IC-SPECIFICATION
TDA 6060XS, TDA 6060G
The reproduction, transmission or use of this document or its contents is not permitted without express written authority. Offenders will be liable for damages.All rights, including rights
created by patent grant or registration of a utility model or design, are reserved.
11.11.1998
V66047-S0894-A100-V3-76D4
page 6
Circuit Description
ments.
The software-switched bidirectional port P2 is a general-purpose open-collector output and can also be
used as an A/D converter input.
In the internal or external 4 MHz reference oscillator mode a test pattern is generated in the reference
divider. With the bít TP in the second control byte this test pattern is switched to the modulator input.
Data are exchanged between the processor and the PLL via the I2C bus. The clock is generated by the
processor (input SCL), while pin SDA functions as an input or output depending on the direction of the data
(open collector, external pull-up resistor). Both inputs have hysteresis and a low-pass characteristic, which
enhance the noise immunity of the I2C bus.
The data from the processor pass through an I2C bus controller. Depending on their function the data are
subsequently stored in registers. If the bus is free, both lines will be in the marking state (SDA, SCL are
HIGH). Each telegram begins with the start condition and ends with the stop condition. Start condition: SDA
goes LOW, while SCL remains HIGH. Stop condition: SDA goes HIGH while SCL remains HIGH. All further
information transfer takes place during SCL = LOW, and the data is forwarded to the control logic on the
positive clock edge.
The table 1 ”bit allocation” should be referred to the following description. All telegrams are transmitted byte-
by-byte, followed by a ninth clock pulse, during which the control logic returns the SDA line to LOW
(acknowledge condition). The first byte is comprised of seven address bits. These are used by the
processor to select the PLL from several peripheral components (chip select). The eighth bit (R/W)
determines whether data are written into (R/W = 0) or read from (R/W = 1) the PLL.
In the data portion of the telegram during a WRITE operation, the first bit of the first or third data byte
determines whether a divider ratio or control information is to follow. In each case the second byte of the
same data type has to follow the first byte.
If the address byte indicates a READ operation, the PLL generates an acknowledge and then shifts out the
status byte onto the SDA line. If the processor generates an acknowledge, a further status byte is output;
otherwise the data line is released to allow the processor to generate a stop condition. The status word
consists of two bits from the TTL input ports, three bits from the A/D converter, the lock flag and the power-
on flag.
Four different chip addresses can be set by appropriate connection of pin CAS (see table 2 ”address
selection”).
When the supply voltage is applied, a power-on reset circuit prevents the PLL from setting the SDA line to
LOW, which would block the bus. The power-on reset flag POR is set at power-on and when VVCCD goes
below 3.2 V. It will be reset at the end of a READ operation.
The lock detector resets the lock flag FL when the width of the charge pump current pulses is greater than
the period of the crystal oscillator (i.e. 250 ns). Hence, when FL = 1, the maximum deviation of the input
frequency from the programmed frequency is given by
f = ± I
P (KVCO / fQ) (C1+C2) / (C1C2)
where IP is the charge pump current, KVCO the VCO gain, fQ the crystal oscillator frequency and C1, C2 the
capacitances in the loop filter (see application circuit). As the charge pump pulses at 62.5 kHz (= fref), it
takes a maximum of 16
s for FL to be reset after the loop has lost lock state.
Once FL has been reset, it is set only if the charge pump pulse width is less than 250 ns for eight
consecutive fref periods. Therefore it takes between 128 and 144 s for FL to be set after the loop regains
the lock state.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TDA6060XS | SPECIALTY CONSUMER CIRCUIT, PDSO28 |
| TDA6118JF/N2/S1 | 1 CHANNEL, VIDEO AMPLIFIER, PSFM9 |
| TDA6160-2X | FM, AUDIO DEMODULATOR, PDSO28 |
| TDA6170X | FM, AUDIO DEMODULATOR, PDSO28 |
| TDA6170X | FM, AUDIO DEMODULATOR, PDSO28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TDA6060XS | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Video-Modulator with PLL |
| TDA6101 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Video output amplifier |
| TDA6101BQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single Video Amplifier |
| TDA6101Q | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Video output amplifier |
| TDA6101Q/N3,112 | 功能描述:視頻放大器 VIDEO OUTPUT AMPLIFIER RoHS:否 制造商:ON Semiconductor 通道數(shù)量:4 電源類型: 工作電源電壓:3.3 V, 5 V 電源電流: 最小工作溫度: 最大工作溫度: 封裝 / 箱體:TSSOP-14 封裝:Reel |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。