參數(shù)資料
型號(hào)： TDA6060G
廠商： SIEMENS A G
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PDSO28
封裝： PLASTIC, TSSOP-28
文件頁(yè)數(shù)： 25/27頁(yè)
文件大?。?/td> 421K
代理商： TDA6060G
SIEMENS
Preliminary IC-SPECIFICATION
TDA 6060XS, TDA 6060G
The reproduction, transmission or use of this document or its contents is not permitted without express written authority. Offenders will be liable for damages.All rights, including rights
created by patent grant or registration of a utility model or design, are reserved.
11.11.1998
V66047-S0894-A100-V3-76D4
page 7
note: MSB is shifted rst.
x = don’t care
Divider ratio:
TDA 6060XS: N = 16384 x n14 + 8192 x n13 + 4096 x n12 + 2048 x n11 + 1024 x n10 + 512 x n9 + 256 x n8
+128 x n7 + 64 x n6 + 32 x n5 + 16 x n4 + 8 x n3 + 4 x n2 + 0 + 0
TDA 6060G: N = 16384 x n14 + 8192 x n13 + 4096 x n12 + 2048 x n11 + 1024 x n10 + 512 x n9 + 256 x n8
+128 x n7 + 64 x n6 + 32 x n5 + 16 x n4 + 8 x n3 + 4 x n2 + 2 + 0
MA0/1:
Address selection (table 2)
PN:
1
negative modulation for video and FM for sound carriers (AudinFM active)
0
positive modulation for video and AM modulation for sound carrier (AudinAM active)
AU 0/1: Audio mode bits and Sound / RF VCO off mode (table 4)
SC0/1:
Sound carrier bits (table 5)
OS:
1
disables VTUNE (for external VCO adjustment)
0
normal PLL operation
FS:
When quartz oscillator is in slave mode:
1
external frequency is 62.5 kHz, for test and special applications
(test pattern and PLL lock in ag FL not available, sound carrier frequencies incorrect)
0
external frequency is 4 MHz
TP:1
1
test pattern generator on
0
normal operation
VG0/1:
Video gain setting (table 6)
MD0/1:
Modulation depth (table 7)
Port P2: 1
open-collector output is active
0
open-collector output is inactive, ADC available
PS0/1:
Picture / sound ratio setting (table 8)
POR:
Power on reset, ag is set at power-on and reset at the end of READ operation
FL:
PLL lock indicator, ag is set when loop is locked
FLV:
Clipping detector, ag is set when clipping duration is longer than 1
sec
A0/1/2:
A/D converter levels when P2 works as input (table 9)
Table 1: Bit Allocation Read/Write Data
MSB
bit6
bit5
bit4
bit3
bit2
bit1
LSB
Ack
Write Data
Address Byte
11000
MA1
MA0
0
Ack
Prog. Divider Byte1
0
n14
n13
n12
n11
n10
n9
n8
Ack
Prog. Divider Byte 2
n7
n6
n5
n4
n3
n2
SC1
SC0
Ack
Control Byte1
1
PN
AU1
AU0
x
OS
FS
Ack
Control Byte 2
TP
VG1
VG0
MD1
MD0
P2
PS1
PS0
Ack
Read Data
Address Byte
11000
MA1
MA0
1
Ack
Status Byte
POR
FL
x
FLV
x
A2
A1
A0
Ack
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