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參數(shù)資料
| 型號： | TDA5360UK |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 光電元器件 |
| 英文描述： | Pre-Amplifier for Hard Disk Drive with MR-Read / Inductive Write Heads |
| 中文描述： | 12 CHANNEL READ WRITE AMPLIFIER CIRCUIT, UUC75 |
| 封裝： | DIE-75 |
| 文件頁數(shù)： | 9/34頁 |
| 文件大?。?/td> | 198K |
| 代理商： | TDA5360UK |
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1998 July 30
Philips Semiconductors
Objective Specification, Revision 2.2
Pre-Amplifier for Hard Disk Drive with
MR-Read / Inductive Write Heads
TDA5360
9
9
FUNCTIONAL DESCRIPTION
9.1
Taking RWN high and programming bits MODE0 and MODE1 (see Reg.09) selects the read mode.
The Head select inputs, in serial register, select the appropriate head.
In read mode, the circuit provides either a constant power bias or a constant current bias that flows from the P to the N
side of the MR section of the head.
The value of the current/power is programmed in Reg. 02 and is referenced by the external resistor, REXT, which is
connected between the REXT pin and GND. The reference voltage on REXT pin is stable over the entire operating
temperature range and process.
The current or power in the MR element is constant over temperature.
The resistance of the MR element, RMR, changes in the presence of a magnetic field and causes a change in the MR
head voltage. The circuit acts as a low-noise differential amplifier to sense this voltage change. The read amplifier
outputs, RDP and RDN, are in phase with the MRP and MRN head ports.
Active READ mode
The read data at pins RDP, RDN can output either voltage or current, depending on how the RVORI bit in Reg.01 is set:
LOW or HIGH respectively.
The polarity convention for current mode is :
“positive” => pin with least current flowing
“negative” => pin with most current flowing
Write current is not present in read mode under any circumstances; either transient or steady state.
The read path includes the following programmable features :
Gain programmation (Reg. 02 and Reg. 03) :
- gain only,
- a combination of gain plus differentiator (therefore HF-gain-boost),
- differentiator only.
The gain is programmable with step of 3dB between 44dB and 50dB.
Input impedance :
With bits RIN1, RIN0 (Reg.01), the input impedance of the readpath can be programmed from 15 to 30
.
Low Pole Frequency :
Bits LFP (Reg.03) allow the programmation of the Low Pole Frequency from 1 to 4 MHz.
Thermal Asperity Detection and Compression :
Thermal Asperity Detector flags an error on FLT line when a thermal disturbance is detected and load the
appropriate error code in Reg. 07. The threshold is programmable via Reg. 05.
Thermal Asperity Compressor extracts the signal from the disturbance. Its thresholds levels and frequency
response are also programmable with Reg.11.
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