參數(shù)資料
型號: TDA5220
廠商: INFINEON TECHNOLOGIES AG
英文描述: ASK/FSK Single Conversion Receiver
中文描述: 詢價/ FSK信號單一轉換接收器
文件頁數(shù): 20/44頁
文件大?。?/td> 719K
代理商: TDA5220
Functional Description
3 - 12
TDA 5220
preliminary
Wireless Components
confidential
Target Specification, October 2001
The demodulator circuit is switched off in case of reception of ASK signals.
3.4.7
Data Filter
The data filter comprises an OP-Amp with a bandwidth of 100kHz used as a
voltage follower and two 100k
=
on-chip resistors. Along with two external
capacitors a 2nd order Sallen-Key low pass filter is formed. The selection of the
capacitor values is described in Section 4.2.
3.4.8
Data Slicer
The data slicer is a fast comparator with a bandwidth of 100 kHz. This allows
for a maximum receive data rate of up to 100kBaud. The maximum achievable
data rate also depends on the IF Filter bandwidth and the local oscillator toler-
ance values. Both inputs are accessible. The output delivers a digital data sig-
nal (CMOS-like levels) for subsequent circuits. A self-adjusting slicer-threshold
on pin 20 its generated by a RC-term. In ASK-mode alternatively a scaled value
of the voltage at the PDO-output (approx. 87%) can be used as the slicer-
threshold. The data slicer threshold generation alternatives are described in
more detail in Section 4.5.
3.4.9
Peak Detector
The peak detector generates a DC voltage which is proportional to the peak
value of the receive data signal. A capacitor is necessary. The input is con-
nected to the output of the RSSI-output of the Limiter, the output is connected
to the
PDO
pin (Pin 26). This output can be used as an indicator for the received
signal strength to use in wake-up circuits and as a reference for the data slicer
in ASK mode. Note that the RSSI level is also output in case of FSK mode.
3.4.10
Bandgap Reference Circuitry
A Bandgap Reference Circuit provides a temperature stable reference voltage
for the device. A power down mode is available to switch off all subcircuits which
is controlled by the PWDN pin (Pin 27) as shown in the following table. The sup-
ply current drawn in this case is typically 50nA.
Table 3-4 PDWN Pin Operating States
PDWN
Operating State
Open or tied to ground
Powerdown Mode
Tied to Vs
Receiver On
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