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參數(shù)資料
| 型號： | TDA4886 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | 140 MHz video controller with I2C-bus |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDIP24 |
| 文件頁數(shù)： | 29/52頁 |
| 文件大?。?/td> | 495K |
| 代理商： | TDA4886 |
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1998 Nov 11
29
Philips Semiconductors
Product specification
140 MHz video controller with I
2
C-bus
TDA4886
Table 4
Subaddress and data byte format
Notes
1.
2.
3.
See Table 3 (Subaddress byte format).
The least significant bit (LSB) of an analog alignment register is defined as AX0 (data bit D0).
Under certain conditions the nominal values lead to nominal colour signals etc. (see note 3 of Chapter
“Characteristics”).
After power-up and after internal power-on reset of the I
2
C-bus the registers are set to the following values:
a) Control bit FPOL to logic 1.
b) Control bits BLH2, BLH1, DISV, DISO and PEDST to logic 0.
c) All other alignment registers to logic 0 (minimum value for control registers).
Data bit.
X means don’t care but for software compatibility with other video ICs with the same slave address, they are
preferably set to logic 0.
4.
5.
FUNCTION
SUBADDRESS
(1)
DATA BYTE
(2)
NOMINAL
VALUE
(3)
DIRECT
MODE
BUFFERED
MODE
D7
(4)
D6
(4)
D5
(4)
D4
(4)
D3
(4)
D2
(4)
D1
(4)
D0
(4)
Control register
Brightness control
Contrast control
OSD contrast
control
Gain control
channel 1
Gain control
channel 2
Gain control
channel 3
Black level
reference channel 1
Black level
reference channel 2
Black level
reference channel 3
00H
01H
02H
03H
80H
81H
82H
83H
X
(5)
X
(5)
X
(5)
X
(5)
X
(5)
X
(5)
X
(5)
X
(5)
BLH2 BLH1 FPOL DISV DISO PEDST
A15
A14
A13
A25
A24
A23
X
(5)
X
(5)
A33
08H
10H
26H
0FH
A12
A22
A32
A11
A21
A31
A10
A20
A30
04H
84H
X
(5)
X
(5)
A45
A44
A43
A42
A41
A40
3FH
05H
85H
X
(5)
X
(5)
A55
A54
A53
A52
A51
A50
3FH
06H
86H
X
(5)
X
(5)
A65
A64
A63
A62
A61
A60
3FH
07H
87H
A77
A76
A75
A74
A73
A72
A71
A70
08H
88H
A87
A86
A85
A84
A83
A82
A81
A80
09H
89H
A97
A96
A95
A94
A93
A92
A91
A90
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