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參數(shù)資料
| 型號(hào)： | TDA4680 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Video processor with automatic cut-off and white level control |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁數(shù)： | 17/28頁 |
| 文件大?。?/td> | 243K |
| 代理商： | TDA4680 |
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1996 Oct 25
17
Philips Semiconductors
Product specification
Video processor with automatic cut-off
and white level control
TDA4680
Notes to the characteristics
The values of the
(B
Y) and
(R
Y) colour difference input signals are for a 75% colour-bar signal.
2.
The pins are capacitively coupled to a low ohmic source, with a recommended maximum output impedance of 600
.
3.
The white potentiometers affect the amplitudes of the RGB output signals including the white measurement pulses.
4.
The RGB outputs at pins 24, 22 and 20 are emitter followers with current sources.
5.
Sandcastle pulses are compared with internal threshold voltages independent of V
P
. The threshold voltages
separate the components of the sandcastle pulse. The particular component is generated when the voltage on pin 14
exceeds the defined internal threshold voltage.
The internal threshold voltages (control bit SC5 = 0) are:
1.5 V for horizontal and vertical blanking pulses
3.5 V for horizontal pulses
6.0 V for the burst key pulse.
The internal threshold voltages (control bit SC5 = 1) are:
1.5 V for horizontal and vertical blanking pulses
3.5 V for the burst key pulse.
6.
A sandcastle pulse with a maximum voltage equal to (V
P
+ 0.7 V) is obtained by limiting a 12 V sandcastle pulse.
7.
Average beam current limiting reduces the contrast, at minimum contrast it reduces the brightness.
8.
Peak drive limiting reduces the RGB outputs by reducing the contrast, at minimum contrast it reduces the brightness.
The maximum RGB outputs are determined via the I
2
C-bus under sub-address 0AH. When an RGB output exceeds
the maximum voltage, peak drive limiting is delayed by one horizontal line.
1.
I
2
C-bus transceiver clock SCL (pin 28)
f
SCL
V
IL
V
IH
I
IL
I
IH
t
L
t
H
t
r
t
f
input frequency range
LOW level input voltage
HIGH level input voltage
LOW level input current
HIGH level input current
clock pulse LOW
clock pulse HIGH
rise time
fall time
0
3.0
10
4.7
4.0
100
1.5
6.0
10
1.0
0.3
kHz
V
V
μ
A
μ
A
μ
s
μ
s
μ
s
μ
s
V
28
= 0.4 V
I
2
C-bus transceiver data input/output SDA (pin 27)
V
IL
V
IH
I
IL
I
IH
I
OL
t
r
t
f
t
SU;DAT
LOW level input voltage
HIGH level input voltage
LOW level input current
HIGH level input current
LOW level output current
rise time
fall time
data set-up time
3.0
10
3.0
0.25
1.5
6.0
10
1.0
0.3
V
V
μ
A
μ
A
mA
μ
s
μ
s
μ
s
V
27
= 0.4 V
V
27
= 0.4 V
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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