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參數(shù)資料
| 型號： | TDA1386T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | DAC |
| 英文描述： | Noise shaping filter DAC |
| 中文描述： | SERIAL INPUT LOADING, 20-BIT DAC, PDSO24 |
| 封裝： | 7.50 MM, PLASTIC, MS-013AD, SOT-137-1, SOP-24 |
| 文件頁數(shù)： | 15/24頁 |
| 文件大?。?/td> | 167K |
| 代理商： | TDA1386T |
1998 Jan 06
15
Philips Semiconductors
Product specification
Noise shaping filter DAC
TDA1386T
AC CHARACTERISTICS (DIGITAL)
V
DDD
= V
DDA
= V
DDO
= 4.5 to 5.5 V; T
amb
=
40 to +85
°
C; all voltages referenced to ground (pins 2, 9 and 23);
unless otherwise specified
.
Note
1.
A clock frequency of up to 96f
s
is possible in the event that a rising edge of BCK occurs while SYSCLK is LOW.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
UNIT
t
W
clock cycle
f
sys
= 256f
s
; normal speed
f
sys
= 128f
s
; double speed
81.3
81.3
22
22
88.6
88.6
156
156
ns
ns
ns
ns
t
CWL
t
CWH
f
sys
LOW level pulse width
f
sys
HIGH level pulse width
Serial input data timing
(see Fig.8)
f
s
word selection input audio sample
frequency
normal speed
double speed
f
sys
= 256f
s
; normal speed
f
sys
= 128f
s
; double speed;
note 1
25
50
44.1
88.2
48
96
64f
s
48f
s
kHz
kHz
kHz
kHz
f
BCK
clock input frequency (data input rate)
t
r
t
f
t
HB
t
LB
t
SU;DAT
t
HD;DAT
t
SU;WS
t
HD;WS
rise time
fall time
bit clock HIGH time
bit clock LOW time
data set-up time
data hold time
word select set-up time
word select hold time
55
55
20
10
20
10
20
20
ns
ns
ns
ns
ns
ns
ns
ns
Microcontroller interface timing
(see Fig.9)
t
L
t
H
t
SU;DC
t
HD;CD
t
SU;CR
input LOW time
Input HIGH time
set-up time DATA to CLOCK
hold time CLOCK to DATA
set-up time CLOCK to RAB
2
2
1
1
1
μ
s
μ
s
μ
s
μ
s
μ
s
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