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參數(shù)資料
| 型號(hào)： | tda 6812-5 |
| 廠商： | SIEMENS AG |
| 英文描述： | TV-Stereo Processor(TV 立體聲處理器) |
| 中文描述： | 電視，立體聲處理器（電視立體聲處理器） |
| 文件頁(yè)數(shù)： | 13/32頁(yè) |
| 文件大小： | 1639K |
| 代理商： | TDA 6812-5 |
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Semiconductor Group
125
TDA 6812-5
Characterstics
V
S
= 12 V;
T
A
= 25
o
C; AF-reference level 0 dB = 250 mVrms unless otherwise defined; in
accordance with test circuit 1.
I
2
C Bus preset:
Start - 84 - 01,3F - 02,3F - 00,00-03,1F - 04,88 - 05,10 - 06,12-07,12-08,12-09,00-Stop
Chip address - Vol
LSl
63 - Vol
LSr
63 - Vol
Pre
0 - Vol
HP
31 - Tone lin - Gain 0 dB - Switch byte I, II,
II, IV
The basic setting for each item in the specifications is always preset; the test conditions only state
settings that differ. Details in italicsare for explanation of the hex codes, for switching bits only set
bits or functions are given.5
Parameter
Symbol
Limit Values
Unit
Test Condition
min.
typ.
max.
Current consumption
I
32
58
85
mA
Signal Section
Max. gain
Max. gain
Max. gain
Max. gain
Max. gain
Max. gain
V
22-1
V
21-3
V
27-1
V
26-3
V
31-1
V
30-3
V
13-1
V
14-3
V
22-3
V
21-3
V
27-3
V
26-3
V
31-3
V
30-3
V
22-1
V
27-1
V
31-1
V
13-3
V
13-1
V
22-1
V
21-3
V
27-1
V
26-3
V
31-1
V
30-3
– 2
– 2
– 2
– 2
– 2
– 2
0
0
0
0
0
0
2
2
2
2
2
2
dB
dB
dB
dB
dB
dB
Gain
Gain
– 2
– 2
0
0
2
2
dB
dB
Max. gain
Max. gain
Max. gain
Max. gain
Max. gain
Max. gain
Max. gain
Max. gain
Max. gain
– 2
– 2
– 2
– 2
– 2
– 2
4
4
4
0
0
0
0
0
0
6
6
6
2
2
2
2
2
2
8
8
8
dB
dB
dB
dB
dB
dB
dB
dB
dB
08,32; Stereo;
V
1
= 0
08,32; Stereo;
V
1
= 0
08,32; Stereo;
V
1
= 0
08,32; Stereo;
V
1
= 0
07,32; Stereo;
V
1
= 0
07,32; Stereo;
V
1
= 0
08,32; Stereo;
V
3
= 0
08,32; Stereo;
V
3
= 0
07,32; Stereo;
V
3
= 0
06,32; Stereo
V
1
= 0
06,32; Stereo
V
3
= 0
09,01; 6 dB
09,01; 6 dB
09,01; 6 dB
09,01; 6 dB
09,01; 6 dB
09,01; 6 dB
Gain
Gain
– 2
4
0
6
2
8
dB
dB
Max. gain
Max. gain
Max. gain
Max. gain
Max. gain
Max. gain
4
4
4
4
4
4
6
6
6
6
6
6
8
8
8
8
8
8
dB
dB
dB
dB
dB
dB
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