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參數(shù)資料
| 型號： | TCM809RENB |
| 廠商： | TelCom Semiconductor, Inc. |
| 英文描述： | 3-PIN UP RESET MONITORS |
| 中文描述： | 3引腳復(fù)位監(jiān)測儀 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大?。?/td> | 60K |
| 代理商： | TCM809RENB |
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TELCOM SEMICONDUCTOR, INC.
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PRELIMINARY INFORMATION
TCM809
TCM810
3-PIN
μ
P RESET MONITORS
valid to V
CC
= 0V, a pull-down resistor must be connected
from RESET to ground to discharge stray capacitances and
hold the output low (Figure 2). This resistor value, though
not critical, should be chosen such that it does not apprecia-
bly load RESET under normal operation (100k
will be
suitable for most applications). Similarly, a pull-up resistor to
V
CC
is required for the TCM810 to ensure a valid high
RESET for V
CC
below 1.0V.
Processors With Bidirectional I/O Pins
Some
μ
P's (such as Motorola 68HC11) have bidirec-
tional reset pins. Depending on the current drive capability
of the processor pin, an indeterminate logic level may result
if there is a logic conflict. This can be avoided by adding a
4.7k resistor in series with the output of the TCM809/810
(Figure 3). If there are other components in the system
which require a reset signal, they should be buffered so as
not to load the reset line. If the other components are
required to follow the reset I/O of the
μ
P, the buffer should
be connected as shown with the solid line.
APPLICATIONS INFORMATION
V
CC
Transient Rejection
The TCM809/810 provides accurate V
CC
monitoring
and reset timing during power-up, power-down, and brown-
out/sag conditions, and rejects negative-going transients
(glitches) on the power supply line. Figure 1 shows the
maximum transient duration vs. maximum negative excur-
sion (overdrive) for glitch rejection. Any combination of
duration and overdrive which lies
under
the curve will
not
generate a reset signal. Combinations above the curve are
detected as a brownout or power-down. Transient immunity
can be improved by adding a capacitor in close proximity to
the V
CC
pin of the TCM809/810.
RESET Signal Integrity During Power-Down
The TCM809 RESET output is valid to V
CC
= 1.0V.
Below this voltage the output becomes an "open circuit" and
does not sink current. This means CMOS logic inputs to the
μ
P will be floating at an undetermined voltage. Most digital
systems are completely shutdown well above this voltage.
However, in situations where RESET must be maintained
Figure 2. Ensuring RESET Valid to V
CC
= 0V
Figure 1. Maximum Transient Duration vs.
Overdrive for Glitch Rejection at 25
°
C
Figure 3. Interfacing to Bidirectional Reset I/O
RESET COMPARATOR OVERDRIVE,
(VTH - VCC (mV)
400
240
160
320
80
0
1
10
100
1000
M
μ
s
T
A
= +25
°
C
V
TH
Duration
Overdrive
V
CC
TCM8xxLM
TCM8xxR/S/T
TCM809
V
CC
V
CC
R1
100k
RESET
GND
TCM809
V
CC
RESET
GND
RESET
GND
BUFFERED RESET
TO OTHER SYSTEM
COMPONENTS
BUFFER
μ
P
4.7k
V
CC
V
CC
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TCM810RENB | 3-PIN UP RESET MONITORS |
| TCM809LENB | 3-PIN UP RESET MONITORS |
| TCM809MENB | 3-PIN UP RESET MONITORS |
| TCM810MENB | 3-PIN UP RESET MONITORS |
| TCM810LENB | 3-PIN UP RESET MONITORS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TCM809RENB713 | 功能描述:監(jiān)控電路 Microprocessor 2.63V RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| TCM809RENB713 | 制造商:Microchip Technology Inc 功能描述:RESET MONITOR 2.63V SOT-23B-3 809 |
| TCM809RENB713-CUT TAPE | 制造商:Microchip 功能描述:TCM809 Series 2.63 V 140 ms 3-Pin Microcontroller Reset Monitor - SOT23B-3 |
| TCM809RENB713G | 制造商:Microchip Technology 功能描述:Processor Supervisor 2.63V 2.5V/3V/3.3V/5V 3-Pin SOT-23B T/R |
| TCM809RVB713 | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:3-Pin Microcontroller Reset Monitors |
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