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參數(shù)資料
| 型號(hào)： | TCM5030T |
| 元件分類(lèi)： | 模擬信號(hào)調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, CQCC32 |
| 封裝： | 0.420 X 0.420 INCH, 1.02 MM PITCH, WINDOWED, CERAMIC, QFN-32 |
| 文件頁(yè)數(shù)： | 12/17頁(yè) |
| 文件大?。?/td> | 311K |
| 代理商： | TCM5030T |
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TCM5030T
2002-01-31
4
Pin Configuration
Pin No.
Symbol
I/O
Function
1
AVDD
Analog power supply. VDD = 2.8 V ± 0.2 V
2
SCLK
I
Serial clock input for commands
3
SDATA
I
Serial data input for commands
4
EN
I
Data enable input for commands
5
DVSSIO
Digital I/O VSS
6
DATACLK
O
Data clock output (half of master clock)
7
DVDDIO
Digital I/O power supply
8
DATA0
I/O
AD output (LSB)
9
DATA1
I/O
AD output
10
DATA2
I/O
AD output
11
DATA3
I/O
AD output
12
DATA4
I/O
AD output
13
DATA5
I/O
AD output
14
DATA6
I/O
AD output
15
DATA7
I/O
AD output
16
DATA8
I/O
AD output
17
DATA9
I/O
AD output (MSB)
18
DVSS
Digital VSS
19
MCK
I
Master clock input
20
DVDD
Digital power supply. 2.8 V
± 0.2 V
21
TEST1
TEST terminal 1
22
DSTOP
I
Read stop control input
H: Active
L: Read stop
23
VRR (VD)
I/O
Vertical timing start pulse input/VD pulse output
24
ESR
I
Electrical shutter start pulse input
25
HPA (HD)
I/O
Horizontal timing start pulse input/HD pulse output
26
SGMODE
I
Internal/External sync select pin
Pulled low (0 V)
L: HPA, VRR, ESR input
H: HD, VD output
27
TEST2
TEST terminal 2
Must be connected to GND
28
RESET
I
Parameter Mode reset input
Pulled up
L: Level
H: Active reset
29
TEST3
TEST terminal 3
Normally this pin is connected to AVSS (2.2
F) via a bypass capacitor.
30
TEST4
TEST terminal 4
Normally this pin is connected to AVSS (0.1
F) via a bypass capacitor.
31
AVSS
Analog VSS
32
TEST5
TEST terminal 5
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