參數(shù)資料
型號(hào): TCM129C18DW
廠商: Texas Instruments, Inc.
英文描述: ANALOG INTERFACE FOR DSP
中文描述: 模擬接口的數(shù)字信號(hào)處理器
文件頁數(shù): 24/25頁
文件大?。?/td> 389K
代理商: TCM129C18DW
TCM29C13, TCM29C14, TCM29C16, TCM29C17,
TCM129C13, TCM129C14, TCM129C16, TCM129C17
COMBINED SINGLE-CHIP PCMCODEC AND FILTER
SCTS011H – APRIL 1986 – REVISED JULY 1996
24
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
output gain-set design considerations (see Figure 9)
PWRO+ and PWRO– are low-impedance complementary outputs. The voltages at the nodes are:
V
O+
at PWRO+
V
O–
at PWRO–
V
OD
= V
O+
– V
O–
(total differential response)
R1 and R2 are a gain-setting resistor network with the center tap to the GSR input.
A value greater than 10 k
and less than 100 k
for R1 + R2 is recommended because of the following:
The parallel combination of R1 + R2 and R
L
sets the total loading.
The total capacitance at the GSR input and the parallel combination of R1 and R2 define a time constant
that has to be minimized to avoid inaccuracies.
V
A
represents the maximum available digital milliwatt output response (V
A
= 3.006 Vrms).
VOD = A
×
VA
where A =
1 + (R1/R2)
4 + (R1/R2)
PWRO+
GSR
PWRO–
2
4
3
R1
R2
VOD
VO
RL
PCM IN
TCM129C13
TCM129C14
TCM129C16
TCM129C17
TCM29C13
TCM29C14
TCM29C16
TCM29C17
VO–
Digital Milliwatt
Sequence Per
CCITT G. 711
Pin numbers shown are for the TCM29C13, TCM29C14, TCM129C13, and TCM129C14 package only.
Figure 10. Gain-Setting Configuration
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