
TCM29C13, TCM29C14, TCM29C16, TCM29C17,
TCM129C13, TCM129C14, TCM129C16, TCM129C17
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS011G – APRIL 1986 – REVISED JULY 1996
19
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
fixed-data-rate timing (see Figure 8)
Fixed-data-rate timing is selected by connecting DCLKR to V
BB
and uses master clocks CLKX and CLKR,
frame-synchronizer clocks FSX and FSR, and output TSX. FSX and FSR are 8-kHz inputs that set the sampling
frequency and distinguish between signaling and nonsignaling frames by their pulse durations. A frame
synchronization pulse one master-clock period long designates a nonsignaling frame, while a double-length
sync pulse enables the signaling function (TCM29C14 and TCM129C14 only). Data is transmitted on PCM OUT
on the first eight positive transitions of CLKX following the rising edge of FSR. Data is received on PCM IN on
the first eight falling edges of CLKR following FSR. A digital-to-analog (D/A) conversion is performed on the
received digital word, and the resulting analog sample is held on an internal sample-and-hold capacitor until
transferred to the receive filter.
The clock-selection pin (CLKSEL) is used to select the frequency of CLKX and CLKR (TCM29C13, TCM29C14,
TCM129C13, and TCM129C14 only). The TCM29C13, TCM29C14, TCM129C13, and TCM129C14 fixed-
data-rate mode can operate with frequencies of 1.536 MHz, 1.544 MHz, or 2.048 MHz. The TCM29C16,
TCM29C17, TCM129C16, and TCM129C17 fixed-data-rate mode operates at 2.048 MHz only.
1
192/193/256
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
TS1X
Other
Time Slots
TS1X
Transmit Signal Frame
Don’t Care
Don’t Care
Valid
B1B2B3B4B5B6B7B8
B1B2B3B4B5B6
B7B8SIGX
1
192/193/256
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
TS1R
Other
Time Slots
TS1R
Receive Signal Frame
Previous Value
B1B2B3B4B5B6B7B8
B1B2B3B4B5B6B7B8
SIGR
9
192/193/256
New Value
CLKX
FSX
PCM OUT
TSX
SIGX
CLKR
FSR
PCM IN
SIGR
Figure 8. Signaling Timing (Fixed-Data-Rate Only)