- 您現在的位置：買賣IC網 > PDF目錄382579 > TCM129C14A (Texas Instruments, Inc.) Combined Single-Chip PCM Codec And Filter(單片PCM編碼譯碼器和濾波器) PDF資料下載
參數資料
| 型號： | TCM129C14A |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | Codec |
| 英文描述： | Combined Single-Chip PCM Codec And Filter(單片PCM編碼譯碼器和濾波器) |
| 中文描述： | 結合單芯片的PCM編解碼器和過濾器（單片的PCM編碼譯碼器和濾波器） |
| 文件頁數： | 11/25頁 |
| 文件大小： | 392K |
| 代理商： | TCM129C14A |
TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TC,129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCMCODEC AND FILTER
SCTS030E – AUGUST 1989 – REVISED OCTOBER 1996
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
receive timing requirements over recommended ranges of supply voltages and operating free-air
temperature, variable-data-rate mode (see Figure 6)
MIN
MAX
UNIT
td(TSDR)
td(FSR)
tsu(PCM IN)
th(PCM IN)
tc(DCLKR)
t(SER)
NOTE 9: tFSLR minimum requirement overrides the td(TSDR) maximum requirement for 64-kHz operation.
64-kbit operation timing requirements over recommended ranges of supply voltage and operating free-air
temperature, variable-data-rate mode
Time-slot delay time from DCLKR (see Note 9)
140
td(DCLKR)–140
tc(CLK)–100
ns
Frame-sync delay time
100
ns
Receive data setup time
50
ns
Receive data hold time
60
ns
Data clock period
488
15620
ns
Time-slot end receive time
0
ns
MIN
488
MAX
UNIT
ns
tFSLX
tFSLR
tw(DCLK)
Transmit frame-sync minimum down time
FSX = TTL high for remainder of frame
Receive frame-sync minimum down time
1952
ns
μ
s
Pulse duration, data clock
10
switching characteristics
delay time over recommended ranges of supply voltage and operating free-air temperature, fixed-data-rate
mode (see Figure 3 and 4)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
tpd1
From rising edge of transmit clock to bit 1 data valid at PCM OUT (data enable
time on time-slot entry) (see Note 10)
CL = 0 to 100 pF
0
145
ns
tpd2
From rising edge of transmit clock bit n to bit n data valid at PCM OUT (data
valid time)
CL = 0 to 100 pF
0
145
ns
tpd3
From falling edge of transmit clock bit 8 to bit 8 Hi-Z at PCM OUT (data float time
on time-slot exit) (see Note 10)
CL = 0
60
215
ns
tpd4
From rising edge of transmit clock bit 1 to TSX active (low) (time-slot enable
time)
CL = 0 to 100 pF
0
145
ns
tpd5
From falling edge of transmit clock bit 8 to TSX inactive (high) (time-slot disable
time) (see Note 10)
CL = 0
60
190
ns
tpd6
From rising edge of channel time slot to SIGR update (TCM29C14A and
TCM129C14A only)
0
2
μ
s
NOTE 10: Timing parameters tpd1, tpd3, and tpd5 are referenced to the high-impedance state.
delay time over recommended ranges of operating conditions, variable-data-rate mode (see Note 11 and
Figure 5)
PARAMETER
TEST CONDITIONS
MIN
MAX
100
UNIT
ns
tpd7
tpd8
tpd9
tpd10
NOTE 11: Timing parameters tpd8 and tpd9 are referenced to the high-impedance state.
Delay time from DCLKX
0
Delay from time-slot enable to PCM OUT
CL = 0 to 100 pF
0
50
ns
Delay from time-slot disable to PCM OUT
0
80
ns
Delay time from FSX
td(TSDX) = 80 ns
0
140
ns
相關PDF資料 |
PDF描述 |
|---|---|
| TCM129C16A | Combined Single-Chip PCM Codec And Filter(單片PCM編碼譯碼器和濾波器) |
| TCM129C16AN | COMBINED SINGLE-CHIP PCM CODEC AND FILTER |
| TCM3105DJE | FSK MODEM |
| TCM3105DNL | FSK MODEM |
| TCM3105 | FSK MODEM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TCM129C14DW | 制造商:TI 制造商全稱:Texas Instruments 功能描述:COMBINED SINGLE-CHIP PCM CODEC AND FILTER |
| TCM129C16 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:COMBINED SINGLE-CHIP PCM CODEC AND FILTER |
| TCM129C16A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:COMBINED SINGLE-CHIP PCM CODEC AND FILTER |
| TCM129C16ADW | 制造商:TI 制造商全稱:Texas Instruments 功能描述:COMBINED SINGLE-CHIP PCM CODEC AND FILTER |
| TCM129C16AN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:COMBINED SINGLE-CHIP PCM CODEC AND FILTER |
發(fā)布緊急采購，3分鐘左右您將得到回復。