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參數(shù)資料
| 型號： | TC9WMA1FK |
| 廠商： | Toshiba Corporation |
| 英文描述： | TOSHIBA CMOS Digital Integrated Circuits Silicon Monolithic |
| 中文描述： | 東芝的CMOS數(shù)字集成電路硅單片 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大小： | 189K |
| 代理商： | TC9WMA1FK |
TC9WMA1FK
2001-10-16
7
Electrical Characteristics
D.C. Characteristics
(GND 0 V, V
CC
2.7~3.6 V, T
opr
40~85°C)
Characteristics
Symbol
Test Condition
Min
Typ.
Max
Unit
Input current
I
LI
5
A
Output leakage current
I
LO
5
A
High level output voltage
V
OH
V
CC
2.7 V, I
OH
1 mA
V
CC
0.4
V
Low level output voltage
V
OL
V
CC
2.7 V, I
OL
2 mA
0.4
V
Quiescent supply current
I
CC1
(Note1)
5
A
Supply current during read
I
CC2
(Note2)
1.5
mA
Supply current during all
erase/program
I
CC3
(Note3)
1.0
mA
Note 1:
CS
1 (except when busy, however)
Note 2: Current that flows for a period from a fall of the 14th to a fall of the 17th
CLK
pulse when executing the
read instruction.
Note 3: Current that flows while executing the all erase or program instruction.
A.C. Characteristics
(GND 0 V, V
CC
2.7~3.6 V, T
opr
40~85°C)
Characteristics
Symbol
Test Condition
Min
Max
Unit
Maximum clock frequency
f
MAX
0
1
MHz
twCLK (L)
Minimum clock pulse width
twCLK (H)
400
ns
Minimum reset pulse width
t
WRST
1
s
Minimum chip select pulse width
t
WCS
1
s
Reset setup time
t
RSS
RST
setup time when
CS
is
switched over
1
s
Clock setup time
t
CKS
CLK
setup time when
CS
is switched
over
250
ns
CS
setup time
t
CSS
CS
setup time when
CLK
is
switched over
250
ns
t
pLH
t
pHL
t
pZH
t
pZL
Time from
CLK
switchover until valid
data is output
250
Propagation delay time
(Note4)
t
pLZ
t
pHZ
Time from
CS
switchover until output
data goes Hi-Z
500
ns
Input data setup time
t
s
Input data setup time when
CLK
is
switched over
250
ns
Input data hold time
t
h
Input data hold time when
CLK
is
switched over
250
ns
Note 4: C
L
100 pF, R
L
1 k
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