參數(shù)資料
型號(hào)： TC94A04AFD
廠商： Toshiba Corporation
英文描述： 1 CHIP AUDIO DIGITAL PROCESSOR
中文描述： 1芯片音頻數(shù)字處理器
文件頁(yè)數(shù)： 11/42頁(yè)
文件大?。?/td> 565K
代理商： TC94A04AFD
TC94A04AF/AFD
2001-11-15
11
2.2
I
2
C Bus Mode
When I2CS
=
“H”, data can be transmitted or received in I
2
C bus mode.
When the CS signal is Low, control from the microcontroller is enabled.
In I
2
C mode, the CS signal can be used fixed to “L”. The IFCK signal is the transmit/receive clock.
The IFDI signal is the data.
The TC94A04AF/AFD loads the IFDI data on the IFCK signal rising edge.
When CS
=
“H”, IFCK and IFD signal are don't care.
2.2.1 Setting Registers
The registers are set by command data using the IFDI signal.
The first byte after the I
2
C address (
=
32h) is a command, which differs for each register. The data
sent after that are fixed to two bytes. Both command and data are sent starting from the MSB in I
2
C
format.
The data loaded internally every two bytes. Note that commands or data that must be switched on
the SYNC signal, such as the RUN command (command-44h) or the IFF flag (command-4Ah), must be
synchronized with the SYNC signal and loaded on that signal.
CS
IFDI
(MCU
→
)
IFCK
C3
C2
C5
C4
C7
C6
C1
C0
A3
A2
A5
A4
A7
A6
A1
A0
D11
D10
D13
D12
D15
D14
D9
D8
An: I
2
C address
Cn: COMMAND
Dn: Data
start
32h
HZ
HZ
HZ
HZ
end
D3
D2
D5
D4
D7
D6
D1
65
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