
TC94A04AF/AFD
2001-11-15
6
Explanation of Block Operations
1. Explanation Pin Operations
Pin No.
TC94A
04AF
TC94A
04AFD
(Note 3)
Symbol
Function
2
3
3
4
XI
XO
Master mode: Connect the crystal oscillator
Slave mode: Supplies an external master clock to XI.
Master clock is 768 fs. Each master-clock frequency to fs is as follows.
fs
768 fs
32 kHz
24.576 MHz
44.1 kHz
33.868 MHz
48 kHz
36.864 MHz
96 kHz
36.864 MHz
1, 4 to 25 2, 5 to 35
Omitted
26
37
V
DDR
Power pin for delay RAM
27
38
GNDR
Ground pin for delay RAM
28
39
SYNC
Program SYNC signal input pin
29
40
ELRI/O
LR clock pin for serial data input (DIN)/serial data output (DOUT).
When you carry out a slave operation to a serial input/output data, please set it as an input.
And when you carry out a master operation, please set it as an output (command 43h: SIOS).
Output frequency can perform selection of 1 fs/2 fs by ELRQS (command: 40h).
30
41
EBCI/O
Bit clock pin for serial data input (DIN)/serial data output (DOUT).
When you carry out a slave operation to a serial input/output data, please set it as an input.
And when you carry out a master operation, please set it as an output (command 43h: SIOS).
Output frequency can be select as follows by EBCQS (command: 40h).
EBCQS [1:0]
Output Frequency
0
32 fs
1
64 fs
2
128 fs
3
for test
31
32
33
43
45
46
DIN2
DIN1
DIN0
Serial data input pin. The serial data of a total of 6-channels can be inputted. Switching of the
number of channel is set by CHSI (command: 42h). Moreover, switching of master/slave
function is set by SIS (command: 42h)
34
48
DOUT
Serial data output pin. Connected to internal register for output in DSP block.
The internal register connected is set up by CHSO (command: 43h).
35
49
V
DD
Power pin
36
50
RST
Reset pin. “L” at initialization.
Note 3: In case of TC94A04AFD, these are NC pins as below. Normally open, otherwise it connects to V
DD
or GND.
6, 10, 12, 16, 19, 22, 29, 31, 34, 36, 42, 44, 47, 51, 56, 62 to 64, 73, 77 pins.