參數(shù)資料
型號: TC9444F
廠商: Toshiba Corporation
英文描述: Single-Chip karaoke IC II
中文描述: 單芯片集成電路二卡拉OK
文件頁數(shù): 7/29頁
文件大?。?/td> 315K
代理商: TC9444F
TC9444F
2002-01-11
7
The microcontroller interface RLS bit controls the polarity of the input/output channel clock (LRCKI, LRCKO).
Table 2.3 Channel Clock Polarity
RLS
Operation
0
L-channel data input/output when LRCKI and LRCKO
“H”
1
L-channel data input/output when LRCKI and LRCKO
“L”
Figure 2.1 Data Input Formats (BCK 64 fs)
a) (IBIT3, IBIT2, IBIT1) (0, 0, 0): MSB first, Right-Justified mode, 16-bit data
LSB
0
LSB
0
MSB
15
LSB
0
MSB
15
SDI
LRCKI
BCKI
LSB
0
LSB
0
MSB
17
LSB
0
MSB
17
SDI
LRCKI
BCKI
LSB
0
LSB
0
MSB
19
LSB
0
MSB
19
SDI
LRCKI
BCKI
LSB
0
LSB
0
MSB
23
LSB
0
MSB
23
SDI
LRCKI
BCKI
MSB
23
LSB
0
MSB
23
LSB
0
MSB
23
SDI
LRCKI
BCKI
b) (IBIT3, IBIT2, IBIT1) (0, 0, 1): MSB first, Right-Justified mode, 18-bit data
c) (IBIT3, IBIT2, IBIT1) (0, 1, 0): MSB first, Right-Justified mode, 20-bit data
d) (IBIT3, IBIT2, IBIT1) (0, 1, 1): MSB first, Right-Justified mode, 24-bit data
e) (IBIT3, IBIT2, IBIT1) (1, 0, 0): IIS-compatible, 24 bits max
Note 3: In either mode, sections where “SDI” is omitted are don’t care (no internal data loading).
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