參數(shù)資料
型號: TC9400COD
元件分類: 模擬專用變換器
英文描述: VOLTAGE-FREQUENCY CONVERTER, 0.1 MHz, PDSO14
封裝: SOIC-14
文件頁數(shù): 25/28頁
文件大?。?/td> 545K
代理商: TC9400COD
TC9400/9401/9402
DS21483D-page 6
2007 Microchip Technology Inc.
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
PIN FUNCTION TABLE
2.1
Bias Current (IBIAS)
An external resistor, connected to VSS, sets the bias
point for the TC9400. Specifications for the TC9400 are
based on RBIAS = 100 kΩ ±10%, unless otherwise
noted.
Increasing the maximum frequency of the TC9400
beyond 100 kHz is limited by the pulse width of the
pulse output (typically 3 s). Reducing RBIAS will
decrease the pulse width and increase the maximum
operating frequency, but linearity errors will also
increase. RBIAS can be reduced to 20 kΩ, which will
typically produce a maximum full scale frequency of
500 kHz.
2.2
Zero Adjust
This pin is the non-inverting input of the operational
amplifier. The low frequency set point is determined by
adjusting the voltage at this pin.
2.3
Input Current (IIN)
The inverting input of the operational amplifier and the
summing junction when connected in the V/F mode. An
input current of 10
μA is specified, but an over range
current up to 50
μA can be used without detrimental
effect to the circuit operation. IIN connects the summing
junction of an operational amplifier. Voltage sources
cannot be attached directly, but must be buffered by
external resistors.
2.4
Voltage Capacitor (VREF Out)
The charging current for CREF is supplied through this
pin. When the op amp output reaches the threshold
level, this pin is internally connected to the reference
voltage and a charge, equal to VREF x CREF, is removed
from the integrator capacitor. After about 3
μsec, this pin
is internally connected to the summing junction of the
op amp to discharge CREF. Break-before-make switch-
ing ensures that the reference voltage is not directly
applied to the summing junction.
2.5
Voltage Reference (VREF)
A reference voltage from either a precision source, or
the VSS supply is applied to this pin. Accuracy of the
TC9400 is dependent on the voltage regulation and
temperature characteristics of the reference circuitry.
Since the TC9400 is a charge balancing V/F converter,
the reference current will be equal to the input current.
For this reason, the DC impedance of the reference
voltage source must be kept low enough to prevent
linearity errors. For linearity of 0.01%, a reference
impedance of 200
Ω or less is recommended. A 0.1 F
bypass capacitor should be connected from VREF to
ground.
Pin No.
Symbol
Description
1IBIAS
This pin sets bias current in the TC9400. Connect to VSS through a 100 kΩ resistor.
2
ZERO ADJ
Low frequency adjustment input.
3IIN
Input current connection for the V/F converter.
4VSS
Negative power supply voltage connection, typically -5V.
5VREF OUT
Reference capacitor connection.
6
GND
Analog ground.
7VREF
Voltage reference input, typically -5V.
8
PULSE FREQ
OUT
Frequency output. This open drain output will pulse LOW each time the Freq.
Threshold Detector limit is reached. The pulse rate is proportional to input voltage.
9OUTPUT
COMMON
Source connection for the open drain output FETs.
10
FREQ/2 OUT
This open drain output is a square wave at one-half the frequency of the pulse output
(Pin 8). Output transitions of this pin occur on the rising edge of Pin 8.
11
THRESHOLD
DETECTOR
Input to the Threshold Detector. This pin is the frequency input during F/V operation.
12
AMPLIFIER OUT Output of the integrator amplifier.
13
NC
No internal connection.
14
VDD
Positive power supply connection, typically +5V.
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