參數(shù)資料
型號(hào)： TC90A67F
元件分類(lèi)： 畫(huà)面疊加
英文描述： PICTURE-IN-PICTURE IC, PQFP80
封裝： 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80
文件頁(yè)數(shù)： 22/24頁(yè)
文件大?。?/td> 321K
代理商： TC90A67F
TC90A67F
2002-02-06
7
Function
TC90A67F has horizontal and vertical sync separation circuit for sub picture, color demodulation circuit for sub
picture, horizontal and vertical timing generation circuit for main picture, PIP control circuit.
Color demodulation circuit consists of digital circuit, and corresponds to M-NTSC, PAL, M-PAL, N-PAL system. It
is possible to process the sub picture easily, according to adopting system clock of 24 MHz by digital PLL circuit
locked fH. Horizontal and vertical timing generation circuit uses system clock (24 MHz) generated by analog PLL
circuit locked main picture’s fH.
PIP control circuit consists of filter for horizontal and vertical reduction, line memory, field memory and
according to changing horizontal and vertical reduction factors, it is possible to carry out various pip sizes.
1.
ADC, Clamping Circuit
Dynamic range of ADC is 1.32 Vp-p whose voltage is fixed in IC. (top voltage is 2.31 V, bottom voltage is
0.99 V) ADC has pedestal clamp function, base voltage is output from CLMP terminal. The pedestal level
becomes about 1.32 V. (64LSB)
2.
Horizontal and Vertical Sync for Main Picture
It is necessary to input main picture’s H-sync and V-sync at PHD and PVD terminal in order to make
system clock for readout stored data into the internal field memory. PHD and PVD are fitted to 5 V. It can
be inverted the polarity using IICBUS registers WHINV and WNINV at sub address 29hex.
At terminals of IC, polarity of H-sync is positive and V-sync is negative.
The clocks from external VCO are selectable in 24 MHz and 48 MHz, it can be switched by given voltage
to CKPSEL (SDIP: 52 pin, QFP: 57 pin) terminal. (CKPSEL L: 24 MHz, CKPSEL H: 48 MHz)
3.
The System Clock Locked to the Sub Picture’s Horizontal Sync.
The signal converted into the digital environment passes through horizontal sync separation circuit,
horizontal locked circuit, which construct PLL circuit, it makes the system clock locked to the sub picture’s
horizontal sync.
This clock is put in internal VCO and generated the system clock of 24 MHz.
4.
Horizontal Reduction
It is necessary to limit to frequency bandwidth for Y signal and color difference signal concerning PIP
mode. Horizontal reduction is selectable using HWS. (HWS: sub address 10hex)
HWS [1:0]
Horizontal Reduction
Sampling Rate for Y
Sampling Rate for Color Difference
00
1/3
4 MHz
1 MHz
01
1/4
3 MHz
0.75 MHz
10
1/6
2 MHz
0.5 MHz
11
1/8
1.5 MHz
0.375 MHz
In order to horizontal reduction, LPFs are used for Y signal and color difference signal.
It is selectable in two kinds of LPF for Y signal and six kinds of LPF for color difference signal.
相關(guān)PDF資料
PDF描述
TC90A67N PICTURE-IN-PICTURE IC, PDIP64
TC90A80F Y/C SEPARATOR IC, PDSO28
TC90A80N Y/C SEPARATOR IC, PDIP28
TC90A92AFG SPECIALTY CONSUMER CIRCUIT, PQFP100
TC9163AN SPECIALTY ANALOG CIRCUIT, PDIP28
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TC90A69FG(ELP) 功能描述:視頻 IC Multi Color 3Line Comb RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel
TC90A69NG 功能描述:視頻 IC Multi Color 3Line Comb RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel
TC90A80F 制造商:TOSHIBA 制造商全稱(chēng):Toshiba Semiconductor 功能描述:3-Line Digital Comb Filter for VCR, YNR/CNR, and Skew Correctors (NTSC)
TC90A80N 制造商:TOSHIBA 制造商全稱(chēng):Toshiba Semiconductor 功能描述:3-Line Digital Comb Filter for VCR, YNR/CNR, and Skew Correctors (NTSC)
TC90A92AFG 制造商:TOSHIBA 制造商全稱(chēng):Toshiba Semiconductor 功能描述:3D comb & Video Decoder
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*