
TC90A66F
2001-06-07
7
Pin
Number
Pin Name
I/O
Function
85
RDAY1
I
Y or sub picture (S system) signal input (field memory read signal/
:)
(Note1)
86
RDAY2
I
Y or sub picture (S system) signal input (field memory read signal/
: )
(Note1)
87
RDAY3
I
Y or sub picture (S system) signal input (field memory read signal/
: )
(Note1)
88
RDAY4
I
Y or sub picture (S system) signal input (field memory read signal/
: )
(Note1)
89
RDAY5
I
Y or sub picture (S system) signal input (field memory read signal/
: )
(Note1)
90
RDAY6
I
Y or sub picture (S system) signal input (field memory read signal/
: )
(Note1)
91
RDAY7
I
Y or sub picture (S system) signal input (field memory read signal/MSB)
(Note1)
92
REN
O
(S system) field memory read enable
93
RRST
O
(S system) field memory read reset
94
EREN
O
(E system) field memory read enable
95
ERRST
O
(E system) field memory read reset
96
RMCK
O
(S/E system) read clock output for field memory
97
RMCKI
I
RMCK input (phase adjustment)
98
VSS
GND
99
RHREF
O
PLL phase comparison output for main picture
100
RCK
I
System clock input for main picture
(Note1)
101
VDD
Power supply (3.3 V)
102
RHD
I
Horizontal sync single input for main picture (It can be inverted using I
2C bus)
(Note1)
103
RVD
I
Vertical sync single input for main picture (It can be inverted using I
2C bus)
(Note1)
104
YS
O
YS signal output
105
KAYS
O
Wallpaper YS signal output
106
HYOJUN
O
Standard/non-standard signal output [standard (L)/non-standard (H)]
107
PWRST
I
System reset input [reset (L)]
108
TIMRST
I
Test reset input [reset (H)/normal (L)]
109
TESO
O
Test monitor output
110
IICNR
I
2C bus noise reduction circuit [on (H)/off (L)]
111
SADSEL
I
Main/sub sub address switch [main (H)/sub (L)]
112
SACN
O
I
2C bus acknowledge output pin
113
VSS
GND
114
SCL
I
2C bus serial clock input
(Note1)
115
SDA
I/O
I
2C bus serial data input (IN)/acknowledge (OUT)
(Note1)
116
TEST4
I
Test input pin (connect to GND)
117
TEST3
I
Test input pin (connect to GND)
118
TEST2
I
Test input pin (connect to GND)
119
TEST1
I
Test input pin (connect to GND)
120
TEST0
I
Test input pin (connect to GND)
121
VDD
Power supply (3.3 V)
122
TIO7
I/O
Test input/output pin (normally, open)
123
TIO6
I/O
Test input/output pin (normally, open)
124
TIO5
I/O
Test input/output pin (normally, open)
125
TIO4
I/O
Test input/output pin (normally, open)
126
TIO3
I/O
Test input/output pin (normally, open)
127
TIO2
I/O
Test input/output pin (normally, open)
Note1: Supports 5 V interface.