參數(shù)資料
型號(hào)： TC90A66F
廠商： Toshiba Corporation
英文描述： PAP/PIP/POP Controller for Wide-Screen TVs (PAL/NTSC)
中文描述： 人民行動(dòng)黨/畫中畫/持久性有機(jī)污染物控制的寬屏幕電視（PAL / NTSC制式）
文件頁數(shù)： 11/39頁
文件大?。?/td> 488K
代理商： TC90A66F
TC90A66F
2001-06-07
11
Pin Number Pin Name
Function
99
RHREF
PLL phase compare output pin for main picture.
The HREF signal obtained by the I/N divider circuit or the phase comparison result of RHD signal. This
signal is used to control the external VCO voltage.
100
RCK
Read clock input pin. It is composing 5 V interface.
Inputs from the external PLL circuit.
Inputs 2400 fH for both 4M and 2M memory.
102
RHD
Horizontal sync signal input pin for main picture (read). Inputs horizontal sync signal from VCD for main
picture. It is composing 5 V interface (negative polarity input). For negative polarity input, set sub
address [28H: RHINV] to non-inversion (L).
Vertical sync signal input pin for main picture (read). Inputs vertical sync signal from VCD for main
picture. It is composing 5 V interface (negative polarity input). For negative polarity input, set sub
address [28H: RVINV] to non-inversion (L).
Main/sub picture switch timing signal output pin. Output amplitude is 3.3 V
p-p
typical. When the YS
signal is High, displays sub picture.
Wallpaper YS signal output.
103
RVD
104
YS
105
KAYS
106
HYOJUN
Standard/non-standard signal output pin [standard (L)/non-standard (H)]
107
PWRST
System reset input pin. When low input, it carries out the reset.
At least 1 V is required as reset duration.
110
IICNR
I
2
C bus noise reduction circuit setting pin.
When set to on (connect to V
DD
), data are latched once by the internal clock, then written to register.
When set to off (connect to GND), data are written to register directly.
111
SADSEL
Sub address of main/sub picture switching pin. [main (H)/sub (L)]
Normally, set to L (enables sub addresses 00h to 7Fh).
112
SACN
I
2
C bus acknowledge output pin.
114
SCL
I
2
C bus serial clock input pin. It is composing 5 V interface.
115
SDA
I
2
C bus serial data input/acknowledge output pin.
It is composing 5 V interface.
136
YOUT
Y signal output pin. Output amplitude is 0.9 V
p-p
typical.
138
IOUT
I signal output pin. Output amplitude is 0.9 V
p-p
typical.
140
QOUT
Q signal output pin. Output amplitude is 0.9 V
p-p
typical.
141 to 142
VB2-1
Bias pin for DAC.
Connect a 0.1
μ
F bypass capacitor between the pins and GND.
143
VREF
DAC reference voltage input pin.
Reference voltage is 2.3 V typical.
144
ADBIAS
Bias pin for ADC.
Connect a 0.1
μ
F bypass capacitor between the pin and AGND.
相關(guān)PDF資料
PDF描述
TC9155AP The TC9155/56AP is an optimum C2MOS IC which has been designed for electronization of tone control of audio equipment with the following features
TC9156AP The TC9155/56AP is an optimum C2MOS IC which has been designed for electronization of tone control of audio equipment with the following features
TC9172AP HIGH SPEED PLL WITH BUILT-IN PRESCALER
TC9227AP HIGH SPEED PLL WITH BUILT-IN PRESCALER
TC9227P HIGH SPEED PLL WITH BUILT-IN PRESCALER
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