參數(shù)資料
型號(hào)： TC820CPL
元件分類： ADC
英文描述： 1-CH DUAL-SLOPE ADC, PDIP40
封裝： PLASTIC, DIP-40
文件頁數(shù)： 26/28頁
文件大?。?/td> 616K
代理商： TC820CPL
2002 Microchip Technology Inc.
DS21476B-page 7
TC820
25
21
PKHOLD
Peak hold input. When connected to VDD, the converter will only update the display if a
new conversion value is greater than the preceding value. Thus, the peak reading will be
stored and held indefinitely. When unconnected, or connected to DGND, the converter
will operate normally. This pin has an internal 5
A pull-down to DGND.
—
22
UR
Under range output. This output will be HIGH when the digital reading is 380
counts or less.
—
23
OR
Over range output. This output will be HIGH when the analog signal input is greater
than full scale. The LCD will display "OL" when the input is over ranged.
26
24
VSS
Negative supply connection. Connect to negative terminal of 9V battery.
27
25
COM
Analog circuit ground reference point. Nominally 3.3V below VDD.
28
26
CREF+
Positive connection for reference capacitor.
29
27
CREF-
Negative connection for reference capacitor.
30
28
VREF+
High differential reference input connection.
31
29
VREF-
Low differential reference input connection.
32
30
VIN-
Low analog input signal connection.
33
31
VIN+
High analog input signal connection.
34
32
VBUFF
Buffer output. Connect to integration resistor.
35
33
CAZ
Auto-zero capacitor connection.
36
34
VINT
Integrator output. Connect to integration capacitor.
—35
EOC/
HOLD
Bi-directional pin. Pulses low (i.e., from V
DD to DGND) at the end of each conversion. If
connected to VDD, conversions will continue, but the display is not updated.
37
36
OSC1
Crystal oscillator (input) connection.
38
37
OSC2
Crystal oscillator (output) connection.
39
38
OSC3
RC oscillator connection.
40
39
VDD
LCD segment drive for "a," "g," and "d" segments of MSD.
TABLE 2-1:
PIN FUNCTION TABLE (CONTINUED)
Pin Number
(40-PDIP)
Pin Number
(44-PQFP)
Symbol
Description
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