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參數(shù)資料
| 型號(hào)： | TC820CPL |
| 廠商： | Microchip Technology Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | 3-3/4 Digit A/D Converter with Frequency Counter and Logic Probe |
| 中文描述： | 3-3/4位A / D轉(zhuǎn)換頻率計(jì)數(shù)器和邏輯轉(zhuǎn)換的探討 |
| 文件頁(yè)數(shù)： | 8/22頁(yè) |
| 文件大?。?/td> | 275K |
| 代理商： | TC820CPL |
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3-156
TELCOM SEMICONDUCTOR, INC.
3-3/4 A/D CONVERTER WITH
FREQUENCY COUNTER
AND LOGIC PROBE
TC820
GENERAL THEORY OF OPERATION
Dual-Slope Conversion Principles
The TC820 analog-to-digital converter operates on the
principle of dual-slope integration. An understanding of the
dual-slope conversion technique will aid the user in follow-
ing the detailed TC820 theory of operation following this
section. A conventional dual-slope converter measurement
cycle has two distinct phases:
(1) Input Signal Integration
(2) Reference Voltage Integration (Deintegration)
Referring to Figure 2, the unknown input signal to be
converted is integrated from zero for a fixed time period
(t
INT
), measured by counting clock pulses. A constant
reference voltage of the opposite polarity is then integrated
until the integrator output voltage returns to zero. The
reference integration (deintegration) time (T
DEINT
) is then
directly proportional to the unknown input voltage (V
IN
).
In a simple dual-slope converter, a complete conver-
sion requires the integrator output to "ramp-up" from zero
and "ramp-down" back to zero. A simple mathematical
equation relates the input signal, reference voltage, and
integration time:
9V
L
A
B
B
O
A
B
P
A
B
B
B
B
H
A
10 11 12 13 14 15
17
9
8
7
6
5
4
3
2
1
LOGIC HIGH
LOGIC LOW
OVERRANGE
PKHOLD
LOW BATT
FREQ/
VOLTS
LOGIC
V+
IN
DP0/LO
DP1/HI
DGND
NC
A
COM
BUZ OUT
BUZ IN
PK HOLD
REFC–
28
0.1
μ
F
30
31
27
40
26
22
23
25
OSC1
37
OSC2 OSC3VBUFF
38
470
k
CAZ
VINT
VDD
VSS
V+
REF
V–
REF
TC820
C+
REF
29
24
18
33
32
16
19
20
21
V–
IN
39
34
35
36
40kHz
NC
100
k
0.47
μ
F
0.2
μ
F
22M
NOTE:
Pin numbers are for
40-pin package.
PIEZO
BUZZER
DGND
DGND
VDD
VDD
VDD
1
μ
F
+
VDD
22k
2k
VREF= 200mV
CHANGE
RANGE
TO
SWITCH
S1a
NO DP
S2
DP3
DP2
DP1
DGND
S1e
S1d
LOGIC
FREQ
GND
VIN
VDD
S1c
S1b
S1a
TO SWITCH
S2
100k
0.01
μ
F
VDD
VDD
COM
RANGE/FREQ
+
–
+
–
REF
VOLTAGE
ANALOG
INPUT
SIGNAL
+
–
DISPLAY
SWITCH
DRIVER
CONTROL
LOGIC
I
O
CLOCK
COUNTER
POLARITY CONTROL
PHASE
CONTROL
VIN
VIN
VFULL SCALE
1.2 VFULL SCALE
VARIABLE
REFERENCE
INTEGRATE
TIME
FIXED
SIGNAL
INTEGRATE
TIME
INTEGRATOR
C
COMPARATOR
R
=
=
Figure 2. Basic Dual-Slope Converter
Figure 1. Typical Operating Circuit
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