參數(shù)資料
型號： TC820C/PL
元件分類： ADC
英文描述： 1-CH 3-BIT DUAL-SLOPE ADC, PARALLEL ACCESS, PDIP40
封裝： 0.600 INCH, PLASTIC, DIP-40
文件頁數(shù)： 9/34頁
文件大?。?/td> 435K
代理商： TC820C/PL
2007 Microchip Technology Inc.
DS21476C-page 17
TC820
5.0
TYPICAL APPLICATIONS
5.1
Power Supplies
The TC820 is designed to operate from a single power
supply such as a 9V battery (Figure 5-1). The converter
will operate over a range of 7V to 15V. For battery oper-
ation, analog common (COM) provides a Common
mode bias voltage (see analog common discussion in
the theory of operation section). However, measure-
ments cannot be referenced to battery ground. To do so
will exceed the Negative Common mode voltage limit.
FIGURE 5-1:
Powering the TC820 from a
Single 9V Battery.
A battery with voltage between 3.5V and 7V can be
used to power the TC820, when used with a voltage
doubler, as shown in Figure 5-2. The voltage doubler
uses the TC7660 and two external capacitors. With this
configuration, measurements can be referenced either
to analog common or to battery ground.
FIGURE 5-2:
Powering the TC820 from a
Low Voltage Battery.
5.2
Digital Ground (DGND)
Digital ground is generated from an internal zener
diode (Figure 5-3). The voltage between VDD and
DGND is the internal supply voltage for the digital
section of the TC820. DGND will sink a minimum of
3mA.
DGND establishes the low logic level reference for the
TC820 mode select inputs, and for the frequency and
logic probe inputs. The DGND pin can be used as the
negative supply for external logic gates, such as the
logic
probe
buffers.
To
ensure
correct
counter
operation at high frequency, connect a 1 F capacitor
from DGND to VDD.
DGND also provides the drive voltage for the LCD. The
TC820 40-pin package internally connects the LCD
VDISP pin to DGND, and provides an LCD drive voltage
of about 5VP-P. In the 44-pin package, connecting the
VDISP pin to DGND will provide a 5V LCD drive voltage.
FIGURE 5-3:
DGND and Com Outputs.
5.3
Digital Input Logic Levels
Logic levels for the TC820 digital inputs are referenced
to VDD and DGND. The high level threshold is
VDD – 1.5V, and the low logic level is DGND + 1.5V. In
most cases, digital inputs will be connected directly to
VDD with a mechanical switch. CMOS gates can also
be used to control the logic inputs, as shown in the logic
probe inputs section.
5.4
Clock Oscillator
The TC820 oscillator can be controlled with either a
crystal, or with an inexpensive resistor capacitor
combination. The crystal circuit, shown in Figure 5-4, is
recommended when high accuracy is required in the
Frequency Counter mode. The 40 kHz crystal is a stan-
dard frequency for ultrasonic alarms, and will provide a
1-second time-base for the counter or 2.5 analog-to-
digital conversions per second. Consult the crystal
manufacturer for detailed applications information.
TC820
VIN
VREF-
VDD
VREF+
COM
VIN+
VIN-
VSS
+
–
9V
+
–
VDD
VSS
VREF+
VREF-
TC820
3.5V to 6V
TC7660
VIN+
VIN-
+
–
VIN
10F
3
4
2
8
5
10F
+
COM
+
–
12A
P
TC820
Logic
Section
5V
3.2V
N
VDD
VSS
COM
DGND
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