參數(shù)資料
型號(hào)： TC811CPL
元件分類： ADC
英文描述： 1-CH DUAL-SLOPE ADC, ACCESS, PDIP40
封裝： PLASTIC, DIP-40
文件頁(yè)數(shù)： 9/13頁(yè)
文件大?。?/td> 145K
代理商： TC811CPL
5
3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER
WITH HOLD AND DIFFERENTIAL REFERENCE INPUTS
TC811
where:
VREF = Reference voltage
tINT = Integration Time
tDEINT = Deintegration Time
GENERAL THEORY OF OPERATION
Dual-Slope Conversion Principles
(All Pin Designations Refer to 40-Pin DIP Package)
The TC811 is a dual slope, integrating analog-to-digital
converter. An understanding of the dual slope conversion
technique will aid the user in following the detailed TC811
theory of operation following this section. A conventional
dual slope converter measurement cycle has two distinct
phases:
1) Input Signal Integration
2) Reference Voltage Integration (Deintegration)
Referring to Figure 2, the unknown input signal to be
converted is integrated from zero for a fixed time period
(TINT), measured by counting clock pulses. A constant
reference voltage of the opposite polarity is then integrated
until the integrator output voltage returns to zero. The
reference integration (deintegration) time (TDEINT) is then
directly proportional to the unknown input voltage (VIN).
In a simple dual slope converter, a complete conversion
requires the integrator output to “ramp-up” from zero and
“ramp-down” back to zero. A simple mathematical equation
relates the input signal, reference voltage and integration
time:
30
20
10
0
NORMAL
MODE
REJECTION
(dB)
0.1/T
1/T
10/T
INPUT FREQUENCY
T = MEASUREMENT PERIOD
Figure 2. Basic Dual Slope Converter
+
–
REF
VOLTAGE
ANALOG
INPUT
SIGNAL
+
–
+/–
DISPLAY
SWITCH
DRIVER
CONTROL
LOGIC
INTEGRATOR
OUTPUT
CLOCK
COUNTER
POLARITY CONTROL
PHASE
CONTROL
VIN
VFULL SCALE
1.2 VFULL SCALE
VARIABLE
REFERENCE
INTEGRATE
TIME
FIXED
SIGNAL
INTEGRATE
TIME
INTEGRATOR
C
COMPARATOR
≈
VREF
+
TC811
33
35
240k
10k
31
29
39
40
VREF
–
0.47
F
0.1F
V
–
1
OSC
2
OSC
TO ANALOG COMMON
(PIN 32)
2 CONVERSION/SEC
180k
0.068F
0.01F
ANALOG
INPUT
+
–
C
REF
34
C
REF
+
VIN
+
VIN
–
ANALOG
COMMON
VINT
VBUFF
CAZ
20
21
38
SEGMENT
DRIVE
9–19
22–25
POL
BP
V
+
MINUS SIGN
BACKPLANE
28
LCD
1M
27
30
32
33
36
9V
+
26
20pF
10pF
V +
22M
470k
1
HLDR
0
tINT
∫
1
VREF tDEINT
RINT CINT
VIN(t) dt =
[ ]
For a constant VINT:
VIN = VREF
tDEINT
tINT
Figure 3. Normal-Mode Rejection of
Dual Slope Converter
Figure 1. Typical Operating Circuit
相關(guān)PDF資料
PDF描述
TC811CKW 1-CH DUAL-SLOPE ADC, ACCESS, PQFP44
TC8129CKW 1-CH PROPRIETARY METHOD ADC, PQFP44
TC815CBU 1-CH DUAL-SLOPE ADC, ACCESS, PQFP64
TC815CBU 1-CH DUAL-SLOPE ADC, PQFP64
TC815CBUTR 1-CH DUAL-SLOPE ADC, PQFP64
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