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參數(shù)資料
| 型號： | TC811CPL |
| 廠商： | TelCom Semiconductor, Inc. |
| 元件分類： | 顯示驅(qū)動器 |
| 英文描述： | 3-1/2 DIGIT A/D CONVERTER WITH HOLD AND DIFFERENTIAL REFERENCE INPUTS |
| 中文描述： | 3-1/2位數(shù)的A / D持有和差分基準輸入變換器 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 171K |
| 代理商： | TC811CPL |
3-141
TELCOM SEMICONDUCTOR, INC.
7
6
5
4
3
1
2
8
3-1/2 DIGIT A/D CONVERTER WITH HOLD AND
DIFFERENTIAL REFERENCE INPUTS
TC811
where:
V
REF
= Reference voltage
t
INT
= Integration Time
t
DEINT
= Deintegration Time
GENERAL THEORY OF OPERATION
Dual-Slope Conversion Principles
(All Pin Designations Refer to 40-Pin DIP Package)
The TC811 is a dual slope, integrating analog-to-digital
converter. An understanding of the dual slope conversion
technique will aid the user in following the detailed TC811
theory of operation following this section. A conventional
dual slope converter measurement cycle has two distinct
phases:
1)
Input Signal Integration
2)
Reference Voltage Integration (Deintegration)
Referring to Figure 2, the unknown input signal to be
converted is integrated from zero for a fixed time period
(T
INT
), measured by counting clock pulses. A constant
reference voltage of the opposite polarity is then integrated
until the integrator output voltage returns to zero. The
reference integration (deintegration) time (T
DEINT
) is then
directly proportional to the unknown input voltage (V
IN
).
In a simple dual slope converter, a complete conversion
requires the integrator output to “ramp-up” from zero and
“ramp-down” back to zero. A simple mathematical equation
relates the input signal, reference voltage and integration
time:
INT
∫
R
INT
C
INT
R
INT
C
INT
30
20
10
0
N
0.1/T
1/T
10/T
INPUT FREQUENCY
T = MEASUREMENT PERIOD
Figure 2. Basic Dual Slope Converter
+
–
REF
VOLTAGE
ANALOG
INPUT
SIGNAL
+
–
+/–
DISPLAY
SWITCH
DRIVER
CONTROL
LOGIC
I
O
CLOCK
COUNTER
POLARITY CONTROL
PHASE
CONTROL
VIN
VIN
VFULL SCALE
1.2 VFULL SCALE
VARIABLE
REFERENCE
INTEGRATE
TIME
FIXED
SIGNAL
INTEGRATE
TIME
INTEGRATOR
C
COMPARATOR
≈
≈
V+
TC811
33
C34
35
C+
VIN
240k
10k
31
29
39
40
V–
OSC
μF
0.1μF
1
2
OSC
TO ANALOG COMMON
(PIN 32)
2 CONVERSION/SEC
180k
0.068μF
0.01μF
AINPUT
–
+
+
VIN
–
ANALOG
VINT
VBUFF
CAZ
20
21
38
SEGMENT
DRIVE
9–19
22–25
POL
BP
V+
MINUS SIGN
BACKPLANE
28
LCD
1M
27
30
32
33
26
36
9V
+
20pF
10pF
V+
V+
22M
470k
1
HLDR
0
1
t
REF
t
DEINT
V
(t) dt =
[ ]
t
INT
For a constant V
INT
:
V
IN
= V
REF
t
DEINT
Figure 3. Normal-Mode Rejection of
Dual Slope Converter
Figure 1. Typical Operating Circuit
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