參數(shù)資料
型號： TC80310AWS
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 模擬信號調理
英文描述： SPECIALTY ANALOG CIRCUIT, UUC7
封裝： DIE-7
文件頁數(shù)： 7/32頁
文件大?。?/td> 982K
代理商： TC80310AWS
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
80310
FUNCTIONAL DEVICE OPERATION
STATE MACHINE
LRC mode is active until the detection of phase stop
regulating RPM (fSTOP). In this case, the device goes back to
the pre-excitation mode. If the phase frequency reaches the
LRC disable RPM default (fLRC), the device goes into
regulation without LRC.
REGULATION WITHOUT LRC:
This mode is active when the phase frequency is above
the LRC disable RPM default (fLRC), the first VREG was
reached with LRC.
The excitation is controlled only by the internal comparator
of B+A and VREG. The DC can not be lower than DCMIN.
If the phase frequency goes below the LRC disable RPM
default (fLRC), then the 80310 comes back to the regulation
with LRC mode. If the phase frequency goes below the phase
stop regulating RPM, the device goes to pre-excitation mode.
RE-REGULATION:
The excitation is forced to 100%. This mode is active if
there is no high phase on non active phase (PHx < VPH) in
the previous cycle, until the high phase comes back. At the
end of the 8th cycle, if there is still no high phase, the
regulation mode is set off and the device goes back to the
regulation mode with or without LRC.
B+A is lower than VREG. In any case, DC cannot be lower
than DCMIN.
.
Figure 10. Self-start State Machine
This state machine runs only if self-start option has been
programmed.
STANDBY:
The 80310 is in Standby mode if there is a LIN timeout,
and in absence of alternator rotation (no phase), if power and
reset (POR), or with a LIN MID3C command, if
nvm_lin_special is set.
There is no excitation
The duty cycle (DC) is equal to zero
The device needs a small amount of quiescent current to
feed some functions such as oscillator.
LIN timeout means:
No activity on the LIN bus during a specified time
or on a LIN watchdog timeout during a specified time
WAKE-UP:
This state is reached when an edge is detected on the
phase (Phase voltage > Phase sensitivity)
The logic is out of reset
Ph ase < LR C
R EGUL ATION w LRC
PR E-EXC
No High Ph ase1 in th e
pr ev io us cycle an d P hase
Regu lation is ON
Ph ase
REG ULAT ION
(High Phase1 appears) o r
(1 00% DC du rin g 8 cycles = > Phase
Regu lation set OF F)
REG ULAT ION w/o LRC
No Hig h Ph ase1 in th e
pr eviou s cycle an d Ph ase
Regu lation is ON
P hase
REGU LATION
(High P hase1 ap pear s) or
(10 0% DC d uring 8 cycles =>
Phase Regulation set OFF)
P hase > Start
Phase < Sto p
Phase > LRC
an d first Vreg reached
with LR C
Ph ase < Stop
-
POR
-
L IN Tim eo ut with no Ph ase
-
L IN M ID3 C if n vm _ lin _special
Wake-u p on
Pha se
S tandby
Ed ge on Phase
. Restart tim er 10 0m s
EX C 100% DC
Ph ase > Star t_ aa
. R estart timer 1 00 ms
Hig h Ph ase1
ap pears
Time out 100 m s
Tim e ou t 100 m s
LIN C om m and with V reg <> 1 0.6 V:
-
MID 29 if n vm _ALT1
-
MID 2A if nv m _ALT 2
-
MID 2B if nvm _lin_sp ecial
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