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參數(shù)資料
| 型號： | TC7MZ273FK |
| 廠商： | Toshiba Corporation |
| 英文描述： | Low-Voltage Octal D-Type Flip-Flop with Clear with 5-V Tolerant Inputs and Outputs |
| 中文描述： | 低電壓八路D類觸發(fā)器與Clear翻牌5 V容限輸入和輸出 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 196K |
| 代理商： | TC7MZ273FK |
TC7MZ273FK
2007-10-19
4
Electrical Characteristics
DC Characteristics
(Ta
=
40~85°C)
Characteristics
Symbol
Test Condition
V
CC
(V)
Min
Max
Unit
High level
V
IH
2.7~3.6
2.0
Input voltage
Low level
V
IL
2.7~3.6
0.8
V
I
OH
=
100
μ
A
2.7~3.6
V
CC
0.2
I
OH
=
12 mA
2.7
2.2
I
OH
=
18 mA
3.0
2.4
High level
V
OH
V
IN
=
V
IH
or V
IL
I
OH
=
24 mA
3.0
2.2
I
OL
= 100
μ
A
2.7~3.6
0.2
I
OL
= 12 mA
2.7
0.4
I
OL
= 16 mA
3.0
0.4
Output voltage
Low level
V
OL
V
IN
=
V
IH
or V
IL
I
OL
= 24 mA
3.0
0.55
V
Input leakage current
I
IN
V
IN
=
0~5.5 V
2.7~3.6
±
5.0
μ
A
Power off leakage current
I
OFF
V
IN
/V
OUT
=
5.5 V
0
10.0
μ
A
V
IN
=
V
CC
or GND
2.7~3.6
10.0
Quiescent supply current
I
CC
V
IN
=
3.6~5.5 V
2.7~3.6
±
10.0
Increase in I
CC
per input
Δ
I
CC
V
IN
=
V
CC
0.6 V
2.7~3.6
500
μ
A
AC Characteristics
(Ta
=
40~85°C)
Characteristics
Symbol
Test Condition
V
CC
(V)
Min
Max
Unit
2.7
Maximum clock frequency
f
MAX
Figure 1, Figure 2
3.3
±
0.3
150
MHz
2.7
9.5
Propagation delay time (CK-Q)
t
PLH
t
PHL
Figure 1, Figure 2
3.3
±
0.3
1.5
8.5
ns
2.7
9.5
Propagation delay time ( CLR -Q)
t
PHL
Figure 1, Figure 3
3.3
±
0.3
1.5
8.5
ns
2.7
3.3
Minimum pulse width (CK)
t
w (H)
t
w (L)
Figure 1, Figure 2
3.3
±
0.3
3.3
ns
2.7
3.3
Minimum bus width ( CLR )
t
w (L)
Figure 3
3.3
±
0.3
3.3
ns
2.7
2.5
Minimum set-up time
t
s
Figure 1, Figure 2
3.3
±
0.3
2.5
ns
2.7
1.5
Minimum hold time
t
h
Figure 1, Figure 2
3.3
±
0.3
1.5
ns
2.7
2.5
Minimum removal time
t
rem
Figure 4
3.3
±
0.3
2.0
ns
2.7
Output to output skew
t
osLH
t
osHL
(Note)
3.3
±
0.3
1.0
ns
Note: This parameter is guaranteed by design.
(t
osLH
=
|t
pLHm
t
pLHn
|, t
osHL
=
|t
pHLm
t
pHLn
|)
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| TC7MZ374 | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:LOW-VOLTAGE OCTAL D-TYPE FLIP-FLOP WITH 5V TOLERANT INPUTS AND OUTPUTS |
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