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參數(shù)資料
| 型號(hào)： | TC7MH373FK |
| 廠商： | Toshiba Corporation |
| 英文描述： | Octal D-Type Latch with 3-State Output |
| 中文描述： | 八路D類(lèi)鎖存器與三態(tài)輸出 |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大?。?/td> | 199K |
| 代理商： | TC7MH373FK |
TC7MH373FK
2007-10-19
5
Timing Requirements
(Input: t
r
=
t
f
=
3 ns)
Ta
=
25°C
Ta
=
40~85°C
Characteristics
Symbol
Test Condition
V
CC
(V)
Typ.
Limit
Limit
Unit
3.3
±
0.3
5.0
5.0
Minimum pulse width
(LE)
t
w (H)
5.0
±
0.5
5.0
5.0
ns
3.3
±
0.3
4.0
4.0
Minimum set-up time
t
s
5.0
±
0.5
4.0
4.0
ns
3.3
±
0.3
1.0
1.0
Minimum hold time
t
h
5.0
±
0.5
1.0
1.0
ns
AC Characteristics
(Input: t
r
=
t
f
=
3 ns)
Ta
=
25°C
Ta
=
40~85°C
Characteristics
Symbol
Test Condition
V
CC
(V)
C
L
(pF)
Min
Typ.
Max
Min
Max
Unit
15
7.0
11.0
1.0
13.0
3.3
±
0.3
50
9.5
14.5
1.0
16.5
15
4.9
7.2
1.0
8.5
Propagation delay time
(LE-Q)
t
pLH
t
pHL
5.0
±
0.5
50
6.4
9.2
1.0
10.5
ns
15
7.3
11.4
1.0
13.5
3.3
±
0.3
50
9.8
14.9
1.0
17.0
15
5.0
7.2
1.0
8.5
Propagation delay time
(D-Q)
t
pLH
t
pHL
5.0
±
0.5
50
6.5
9.2
1.0
10.5
ns
15
7.3
11.4
1.0
13.5
3.3
±
0.3
50
9.8
14.9
1.0
17.0
15
5.5
8.1
1.0
9.5
3-state output enable time
t
pZL
t
pZH
R
L
=
1 k
Ω
5.0
±
0.5
50
7.0
10.1
1.0
11.5
ns
3.3
±
0.3
50
9.5
13.2
1.0
15.0
3-state output disable time
t
pLZ
t
pHZ
R
L
=
1 k
Ω
5.0
±
0.5
50
6.5
9.2
1.0
10.5
ns
3.3
±
0.3
50
1.5
1.5
Output to output skew
t
osLH
t
osHL
(Note 1)
5.0
±
0.5
50
1.0
1.0
ns
Input capacitance
C
IN
4
10
10
pF
Bus input capacitance
C
OUT
6
pF
Power dissipation
capacitance
C
PD
(Note 2)
27
pF
Note 1: This parameter is guaranteed by design.
t
osLH
=
|t
pLHm
t
pLHn
|, t
osHL
=
|t
pHLm
t
pHLn
|
Note 2: C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
I
CC (opr)
=
C
PD
V
CC
f
IN
+
I
CC
/8 (per latch)
And the total CPD when n pcs of latch operate can be gained by the following equation:
C
PD
(total)
=
14
+
13
n
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