參數(shù)資料
型號: TC74AC373P_07
廠商: Toshiba Corporation
英文描述: CMOS Digital Integrated Circuit Silicon Monolithic Octal D-Type Latch with 3-State Output
中文描述: CMOS數(shù)字集成電路硅單片八路D類鎖存器與三態(tài)輸出
文件頁數(shù): 4/9頁
文件大小: 242K
代理商: TC74AC373P_07
TC74AC373P/F/FT
2007-10-01
4
Electrical Characteristics
DC Characteristics
Test Condition
Ta = 25°C
Ta =
40 to 85°C
Characteristics
Symbol
V
CC
(V)
Min
Typ.
Max
Min
Max
Unit
High-level input
voltage
V
IH
2.0
3.0
5.5
1.50
2.10
3.85
1.50
2.10
3.85
V
Low-level input
voltage
V
IL
2.0
3.0
5.5
0.50
0.90
1.65
0.50
0.90
1.65
V
I
OH
=
50
μ
A
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
High-level output
voltage
V
OH
V
IN
= V
IH
or
V
IL
I
OH
=
4 mA
I
OH
=
24 mA
I
OH
=
75 mA
(Note)
3.0
4.5
5.5
2.58
3.94
2.48
3.80
3.85
V
I
OL
= 50
μ
A
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
Low-level output
voltage
V
OL
V
IN
= V
IH
or
V
IL
I
OL
= 12 mA
I
OL
= 24 mA
I
OL
= 75 mA
(Note)
3.0
4.5
5.5
0.36
0.36
0.44
0.44
1.65
V
3-state output
off-state current
I
OZ
V
IN
= V
IH
or V
IL
V
OUT
= V
CC
or GND
5.5
±0.5
±5.0
μ
A
Input leakage
current
I
IN
V
IN
= V
CC
or GND
5.5
±0.1
±1.0
μ
A
Quiescent supply
current
I
CC
V
IN
= V
CC
or GND
5.5
8.0
80.0
μ
A
Note:
This spec indicates the capability of driving 50
transmission lines.
One output should be tested at a time for a 10 ms maximum duration.
Timing Requirements
(input: t
r
= t
f
= 3 ns)
Test Condition
Ta =
25°C
Ta =
40 to
85°C
Characteristics
Symbol
V
CC
(V)
Limit
Limit
Unit
Minimum pulse width
(LE)
t
w (H)
3.3 ± 0.3
5.0 ± 0.5
7.0
5.0
7.0
5.0
ns
Minimum set-up time
t
s
3.3 ± 0.3
5.0 ± 0.5
6.0
3.5
6.0
3.5
ns
Minimum hold time
t
h
3.3 ± 0.3
5.0 ± 0.5
1.0
1.0
1.0
1.0
ns
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