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參數(shù)資料
| 型號(hào)： | TC74A7-5.0VCTTRG |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 338K |
| 描述： | IC DGTL THERM SNSR 5.0V SOT23A-5 |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 功能： | 溫度監(jiān)控系統(tǒng)（傳感器） |
| 傳感器類型： | 內(nèi)部 |
| 感應(yīng)溫度： | -40°C ~ 125°C |
| 精確度： | ±3°C（最小值） |
| 拓?fù)洌?/td> | ADC（三角積分型），寄存器庫 |
| 輸出類型： | I²C?/SMBus? |
| 輸出警報(bào)： | 無 |
| 輸出風(fēng)扇： | 無 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SC-74A，SOT-753 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-5 |
| 包裝： | 帶卷 (TR) |
TC74
DS21462C-page 6
?2002 Microchip Technology Inc.
3.0
DETAILED DESCRIPTION
3.1
Functional Description
The TC74 acquires and converts temperature
information from its onboard solid-state sensor with a
resolution of ?癈. It stores the data in an internal
register which is then read through the serial port. The
system interface is a slave SMBus/I
2
C port, through
which temperature data can be read at any time. Eight
SMBus/I
2
C addresses are programmable for the TC74,
which allows for a multi-sensor configuration. Also,
there is low power Standby mode when temperature
acquisition is suspended.
3.1.1
STANDBY MODE
The host is allowed, by the TC74, to put it into a low
power (I
DD
= 5 礎(chǔ), typical) Standby mode. In this
mode, the A/D converter is halted and the temperature
data registers are frozen. The SMBus/I
2
C port, though,
operates normally. Standby mode is enabled by setting
the SHDN bit in the CONFIG register. Table 3-1
summarizes this operation.
TABLE 3-1:
STANDBY MODE OPERATION
3.1.2
SMBUS/I
2
C SLAVE ADDRESS
The TC74 is internally programmed to have a default
SMBus/I
2
C address value of 1001 101b. Seven other
addresses are available by custom order (contact
Microchip Technology Inc.
3.2
Serial Port Operation
The Serial Clock input (SCLK) and bidirectional data
port (SDA) form a 2-wire bidirectional serial port for pro-
gramming and interrogating the TC74. The
conventions used in this bus architecture are listed in
Table 3-2.
TABLE 3-2:
SERIAL BUS CONVENTIONS
All transfers take place under the control of a host, usu-
ally a CPU or microcontroller, acting as the Master. This
host provides the clock signal for all transfers. The
TC74 always operates as a Slave. The serial protocol
is illustrated in Figure 3-1. All data transfers have two
phases and all bytes are transferred MSB first.
Accesses are initiated by a START condition, followed
by a device address byte and one or more data bytes.
The device address byte includes a Read/Write selec-
tion bit. Each access must be terminated by a STOP
condition. A convention called Acknowledge (ACK)
confirms receipt of each byte. Note that SDA can
change only during periods when SCLK is low (SDA
changes while SCLK is high are reserved for START
and STOP conditions).
SHDN Bit
Operating Mode
0
Normal
1
Standby
Term
Explanation
Transmitter The device sending data to the bus.
Receiver
The device receiving data from the bus.
Master
The device which controls the bus initi-
ating transfers (START), generating the
clock and terminating transfers
(STOP).
Slave
The device addressed by the master.
START
A unique condition signaling the begin-
ning of a transfer indicated by SDA
falling (high-low) while SCLK is high.
STOP
A unique condition signaling the end of
a transfer indicated by SDA rising (low-
high) while SCLK is high.
ACK
A Receiver acknowledges the receipt
of each byte with this unique condition.
The Receiver drives SDA low during
SCLK high of the ACK clock-pulse. The
Master provides the clock pulse for the
ACK cycle.
Busy
Communication is not possible
because the bus is in use.
NOT Busy When the bus is idle, both SDA and
SCLK will remain high.
Data Valid The state of SDA must remain stable
during the high period of SCLK in order
for a data bit to be considered valid.
SDA only changes state while SCLK is
low during normal data transfers (see
START and STOP conditions).
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