參數(shù)資料
型號： TC74A23F
廠商： Toshiba Corporation
英文描述： RELAY SWITCH; N RELAY SWITCH; FREQUENCY RANGE: DC-4 GHz; SWICH TYPE: SPDT; FEATURE: FAILSAFE; ACTUATING VOLTAGE: 12; VSWR: 1.20:1 @ 4 GHz
中文描述： 東芝的CMOS數(shù)字集成電路硅單片
文件頁數(shù)： 4/20頁
文件大小： 221K
代理商： TC74A23F
TC94A23F
2002-02-06
12
Pin
Number
Symbol
Pin Name
Function and Operation
Remarks
81
DVSR
R-channel D/A converter block ground pin
82
RO
R-channel data forward rotation output pin
83
DVRR
R-channel reference voltage pin
84
DVDD
D/A converter block power supply pin
85
DVRL
L-channel reference voltage pin
86
LO
L-channel data forward rotation output pin
87
DVSL
CD processor control
input/output
L-channel D/A converter block ground pin
90
RST
Reset input
Device system reset signal input pin.
While the RST is at Low level, reset is
applied. When the RST is at High level, the
CD block is in operation, and the controller
program starts from address 0.
Normally, when 2.7 V or higher voltage is
supplied to the MVDD when at 0 V, system
reset is applied (power-on reset). Fix the pin
to High level.
91
HOLD
Hold mode control
input
Input pin used to request or release hold
state.
Normally, the pin is used for inputting the CD
mode selection signal or battery detection
signal.
Halt states are Clock Stop mode (crystal
oscillator stops oscillation) and Wait mode
(CPU stops). The modes are entered using
the CKSTP and WAIT instructions.
By program, Clock Stop mode can be entered
by detection of Low level on the HOLD pin or
by forced execution. Clock Stop mode can be
released by detection of High level on the
HOLD pin or change in the HOLD pin input.
Executing the CKSTP instruction stops the
clock generator and the CPU, entering
memory backup state. During memory backup
state, current dissipation becomes low (1
mA
or below). The display output and CMOS
output port automatically become Low level.
The N-channel open drain output becomes
off.
Regardless of the HOLD pin input state, Wait
mode is executed and current dissipation
becomes low. Crystal oscillator only on or
CPU operation suspended can be
programmed. When the crystal oscillator only
is on, all displays are at Low level. The other
pins are in Hold state. When CPU operation is
suspended, all states are held except that the
CPU is suspended. Wait mode is released by
a change of the HOLD pin input.
(Note)
To use Backup mode, turn off the
VDD pin (power supply for CD), and
enter Backup mode.
DVDD
VSS
DVSL/DVSR
DVDD
RO/LO
DVRR/DVRL
MVDD
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