參數(shù)資料
型號(hào)： TC7135CBUTR
元件分類： ADC
英文描述： 1-CH DUAL-SLOPE ADC, PQFP64
封裝： PLASTIC, MS-022-BE, MQFP-64
文件頁(yè)數(shù)： 3/24頁(yè)
文件大?。?/td> 471K
代理商： TC7135CBUTR
2004 Microchip Technology Inc.
DS21460C-page 11
TC7135
5.3
BUSY Output
At the beginning of the signal integration phase, BUSY
goes high and remains high until the first clock pulse
after the integrator zero crossing. BUSY returns to the
logic ‘0’ state once the measurement cycle ends in an
overrange condition. The internal display latches are
loaded during the first clock pulse after BUSY and are
latched at the clock pulse end. The BUSY signal does
not go high at the beginning of the measurement cycle,
which starts with the auto-zero cycle.
5.4
OVERRANGE Output
If the input signal causes the reference voltage integra-
tion time to exceed 20,000 clock pulses, the OVER-
RANGE output is set to a logic ‘1’. The OVERRANGE
output register is set when BUSY goes low and is reset
at the beginning of the next reference integration
phase.
5.5
UNDERRANGE Output
If the output count is 9% of full scale or less (-1800
counts), the UNDERRANGE register bit is set at the
end of BUSY. The bit is set low at the next signal
integration phase.
5.6
POLARITY Output
A positive input is registered by a logic ‘1’ polarity
signal. The polarity bit is valid at the beginning of
reference integrate and remains valid until determined
during the next conversion.
The polarity bit is valid even for a zero reading. Signals
less than the converter's LSB will have the signal
polarity determined correctly. This is useful in null
applications.
5.7
Digit Drive Outputs
Digit drive signals are positive-going signals. The scan
sequence is D5 to D1. All positive pulses are 200 clock
pulses wide, with the exception D5, which is 201 clock
pulses wide.
All five digits are scanned continuously, unless an
overrange condition occurs. In an overrange condition,
all digit drives are held low from the final STROBE
pulse until the beginning of the next reference integrate
phase. The scanning sequence is then repeated. This
provides a blinking visual display indication.
5.8
BCD Data Outputs
The binary coded decimal (BCD) bits B8, B4, B2 and B1
are positive-true logic signals. The data bits become
active at the same time as the digit drive signals. In an
overrange condition, all data bits are at a logic ‘0’ state.
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