參數(shù)資料
型號： TC7135CBU
元件分類： ADC
英文描述： 1-CH DUAL-SLOPE ADC, PQFP64
封裝： PLASTIC, MS-022-BE, MQFP-64
文件頁數(shù)： 21/24頁
文件大?。?/td> 471K
代理商： TC7135CBU
TC7135
DS21460C-page 6
2004 Microchip Technology Inc.
3.0
DETAILED DESCRIPTION
All pin designations refer to the 28-pin PDIP package.
3.1
Dual-Slope Conversion Principles
The TC7135 is a dual-slope, integrating A/D converter.
An
understanding
of
the
dual-slope
conversion
technique will aid in following the detailed TC7135
operational theory.
The conventional dual-slope converter measurement
cycle has two distinct phases:
1.
Input signal integration.
2.
Reference voltage integration (de-integration).
The input signal being converted is integrated for a
fixed time period. Time is measured by counting clock
pulses. An opposite polarity constant reference voltage
is then integrated until the integrator output voltage
returns to zero. The reference integration time is
directly proportional to the input signal.
In
a
simple
dual-slope
converter,
a
complete
conversion requires the integrator output to “ramp-up”
and “ramp-down”.
A simple mathematical equation relates the input
signal, reference voltage and integration time:
EQUATION 3-1:
For a constant VIN:
EQUATION 3-2:
The dual-slope converter accuracy is unrelated to the
integrating resistor and capacitor values, as long as
they are stable during a measurement cycle. An
inherent benefit is noise immunity. Noise spikes are
integrated, or averaged, to zero during the integration
periods.
Integrated ADCs are immune to the large conversion
errors that plague successive approximation converters
in high-noise environments (see Figure 3-1).
FIGURE 3-1:
Basic Dual-Slope Converter.
3.2
TC7135 Operational Theory
The TC7135 incorporates a system zero phase and
integrator output voltage zero phase to the normal two-
phase
dual-slope
measurement
cycle.
Reduced
system errors, fewer calibration steps and a shorter
overrange recovery time result.
The TC7135 measurement cycle contains four phases:
1.
System zero.
2.
Analog input signal integration.
3.
Reference voltage integration.
4.
Integrator output zero.
Internal analog gate status for each phase is shown in
TABLE 3-1:
INTERNAL ANALOG GATE STATUS
1
R
INTCINT
------------------------
V
IN T
()DT
0
T
INT
∫
V
REFTDEINT
R
INTCINT
--------------------------------
=
Where:
VREF = Reference voltage
TINT = Signal integration time (fixed)
TDEINT = Reference voltage integration time
(variable)
V
IN
V
REFTDEINT
T
IN T
--------------------------------
=
+
-
REF
Voltage
Analog Input
Signal
+
-
Display
Switch
Drive
Control
Logic
Int
egr
ato
r
Ou
tp
u
t
Clock
Counter
Polarity Control
Phase
Control
VIN
≈ V
REF
Variable
Reference
Integrate
Time
Fixed
Signal
Integrate
Time
Integrator
Comparator
VIN
≈ 1/2 V
REF
Conversion Cycle Phase
SWI
SWRI+SWRI-SWZ
SWR
SW1
SWIZ
Reference Figures
System Zero
—
Closed
—
Input Signal Integration
Closed
—
Reference Voltage Integration
—
Closed*
—
Closed
—
Integrator Output Zero
—
Closed
* Assumes a positive polarity input signal. SWRI would be closed for a negative input signal.
相關PDF資料
PDF描述
TC7135CLI713 1-CH DUAL-SLOPE ADC, PQCC28
TC7135CPIG 1-CH DUAL-SLOPE ADC, PDIP28
TC7135CLI 1-CH DUAL-SLOPE ADC, PQCC28
TC7135CBU 1-CH DUAL-SLOPE ADC, PQFP64
TC7136ACLW 1-CH DUAL-SLOPE ADC, ACCESS, PQCC44
相關代理商/技術參數(shù)
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