參數(shù)資料
型號(hào)： TC7109CLWR
元件分類(lèi)： ADC
英文描述： 1-CH 12-BIT DUAL-SLOPE ADC, PARALLEL ACCESS, PQCC44
封裝： PLASTIC, LCC-44
文件頁(yè)數(shù)： 3/28頁(yè)
文件大?。?/td> 598K
代理商： TC7109CLWR
2002 Microchip Technology Inc.
DS21456B-page 11
TC7109/A
3.2.4
DIRECT MODE
The data outputs (bits 1 through 8, low order bytes; bits
9 through 12, polarity and over range high order bytes)
are accessible under control of the byte and chip
enable terminals as inputs, with the MODE pin at a
LOW level. These three inputs are all active LOW.
Internal pull-up resistors are provided for an inactive
HIGH level when left open. When chip enable is LOW,
a byte enable input LOW will allow the outputs of the
byte to become active. A variety of parallel data
accessing techniques may be used, as shown in the
"Interfacing" section. (See Figure 3-4 and Table 3-1.)
The access of data should be synchronized with the
conversion cycle by monitoring the STATUS output.
This prevents accessing data while it is being updated
and eliminates the acquisition of erroneous data.
FIGURE 3-4:
TC7109A DIRECT MODE
OUTPUT TIMING
TABLE 3-1:
TC7109A DIRECT MODE
TIMING REQUIREMENTS
3.2.5
HANDSHAKE MODE
An alternative means of interfacing the TC7109A to
digital systems is provided when the Handshake Out-
put mode of the TC7109A becomes active in controlling
the flow of data, instead of passively responding to chip
and byte enable inputs. This mode allows a direct inter-
face between the TC7109A and industry standard
UARTs with no external logic required. The TC7109A
provides all the control and flag signals necessary to
sequence the two bytes of data into the UART and ini-
tiate their transmission in serial form when triggered
into the Handshake mode. The cost of designing
remote data acquisition stations is reduced using serial
data transmission to minimize the number of lines to
the central controlling processor.
The MODE input controls the Handshake mode. When
the MODE input is held HIGH, the TC7109A enters the
Handshake mode after new data has been stored in the
output latches at the end of every conversion per-
formed (see Figure 3-7 and Figure 3-8). Entry into the
Handshake mode may be triggered on demand by the
MODE input. At any time during the conversion cycle,
the LOW-to-HIGH transition of a short pulse at the
MODE input will cause immediate entry into the Hand-
shake mode. If this pulse occurs while new data is
being stored, the entry into Handshake mode is
delayed until the data is stable. The MODE input is
ignored in the Handshake mode, and until the con-
verter completes the output cycle and clears the Hand-
shake mode, data updating will be inhibited (see
Figure 3-9).
When the MODE input is HIGH, or when the converter
enters the Handshake mode, the chip and byte enable
inputs become TTL compatible outputs, which provide
the output cycle control signals (see Figure 3-7,
Figure 3-8 and Figure 3-9). The SEND input is used by
the converter as an indication of the ability of the
receiving device (such as a UART) to accept data in the
Handshake mode. The sequence of the output cycle
with SEND held HIGH is shown in Figure 3-7. The
Handshake mode (internal MODE HIGH) is entered
after the data latch pulse (the CE/LOAD, LBEN and
HBEN terminals are active as outputs, since MODE
remains HIGH).
The HIGH level at the SEND input is sensed on the
same HIGH-to-LOW internal clock edge. On the next
LOW-to-HIGH internal clock edge, the high order byte
(bits 9 through 12, POL, and OR) outputs are enabled
and the CE/LOAD and the HBEN outputs assume a
LOW level. The CE/LOAD output remains LOW for one
full internal clock period only; the data outputs remain
active for 1-1/2 internal clock periods; and the high byte
enable remains LOW for 2 clock periods.
Symbol
Description
Min
Typ
Max
Units
tBEA
Byte Enable Width
200
500
—
nsec
tDAB
Data Access Time
from Byte Enable
—
150
300
nsec
tDHB
Data Hold Time from
Byte Enable
—
150
300
nsec
tCEA
Chip Enable Width
300
500
nsec
tDAC
Data Access Time
from Chip Enable
—
200
400
nsec
tDHC
Data Hold Time from
Chip Enable
—
200
400
nsec
= High Impedance
CE/LOAD
As Input
tCEA
tBEA
HBEN
As Input
tDAB
LBEN
As Input
High Byte
Data
Low Byte
Data
Valid
tDAC
tDHC
Data
Valid
Data
Valid
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