參數(shù)資料
型號(hào): TC7109ACLWR
元件分類: ADC
英文描述: 1-CH 12-BIT DUAL-SLOPE ADC, PARALLEL ACCESS, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 28/28頁
文件大?。?/td> 598K
代理商: TC7109ACLWR
2002 Microchip Technology Inc.
DS21456B-page 9
TC7109/A
3.2.3
RUN/HOLD INPUT
With the RUN/HOLD input high, or open, the circuit
operates normally as a dual slope ADC, as shown in
Figure 3-1. Conversion cycles operate continuously
with the output latches updated after zero crossing in
the De-integrate mode. An internal pull-up resistor is
provided to ensure a HIGH level with an open input.
The RUN/HOLD input may be used to shorten conver-
sion time. If RUN/HOLD goes LOW any time after zero
crossing in the De-integrate mode, the circuit will jump
to auto-zero and eliminate that portion of time normally
spent in de-integrate.
If RUN/HOLD stays or goes LOW, the conversion will
complete with minimum time in de-integrate. It will stay
in auto-zero for the minimum time and wait in auto-zero
for a HIGH at the RUN/HOLD input. As shown in
Figure 3-3, the STATUS output will go HIGH, 7 clock
periods after RUN/HOLD is changed to HIGH, and the
converter will begin the integrate phase of the next
conversion.
The RUN/HOLD input allows controlled conversion
interface. The converter may be held at IDLE in auto-
zero with RUN/HOLD LOW. Theconversionis started
when RUN/HOLD goes HIGH, and the new data is
valid when the STATUS output goes LOW (or is trans-
ferred to the UART; see "Handshake Mode"). RUN/
HOLD may now go LOW, terminating de-integrate and
ensuring a minimum auto-zero time before stopping to
wait for the next conversion. Conversion time can be
minimized by ensuring RUN/HOLD goes LOW during
de-integrate, after zero crossing, and goes HIGH after
the hold point is reached.
The required activity on the RUN/HOLD input can be
provided by connecting it to the buffered oscillator out-
put. In this mode, the input value measured determines
the conversion time.
FIGURE 3-1:
CONVERSION TIMING (RUN/HOLD PIN HIGH
Internal Clock
Integrator Output
for Normal Input
Integrator
Saturates
Internal Latch
Integrator Output
for Over Range Input
No Zero Crossing
ZI
AZ
Zero Integrator
Phase forces
Integrator Output
to 0V
Zero Crossing
Occurs
Zero Crossing
Detected
INT
Phase II
Status Output
AZ
Phase I
DE
Phase III
AZ
Fixed
2048
Counts
2048
Counts
Min.
4096
Counts
Max
Number of Counts to Zero Crossing
Proportional to VIN
After Zero Crossing, Analog section will
be in Auto-Zero Configuration
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