參數(shù)資料
型號: TC7109ACKWR
元件分類: ADC
英文描述: 1-CH 12-BIT DUAL-SLOPE ADC, PARALLEL ACCESS, PQFP44
封裝: PLASTIC, QFP-44
文件頁數(shù): 26/28頁
文件大小: 598K
代理商: TC7109ACKWR
2002 Microchip Technology Inc.
DS21456B-page 7
TC7109/A
Note:
All Digital levels are positive true.
3.0
DETAILED DESCRIPTION
(All Pin Designations Refer to 40-Pin DIP.)
3.1
Analog Section
The Typical Application diagram on page 3 shows a
block diagram of the analog section of the TC7109A.
The circuit will perform conversions at a rate deter-
mined by the clock frequency (8192 clock periods per
cycle), when the RUN/HOLD input is left open or con-
nected to V+. Each measurement cycle is divided into
four phases, as shown in Figure 3-1. They are:
(1) Auto-Zero (AZ), (2) Signal Integrate (INT), (3) Ref-
erence De-integrate (DE), and (4) Zero Integrator (ZI).
3.1.1
AUTO-ZERO PHASE
The buffer and the integrator inputs are disconnected
from input high and input low and connected to analog
common. The reference capacitor is charged to the ref-
erence voltage. A feedback loop is closed around the
system to charge the auto-zero capacitor, CAZ,to com-
pensate for offset voltage in the buffer amplifier, inte-
grator, and comparator. Since the comparator is
included in the loop, the AZ accuracy is limited only by
the noise of the system. The offset referred to the input
is less than 10
V.
3.1.2
SIGNAL INTEGRATE PHASE
The buffer and integrator inputs are removed from com-
mon and connected to input high and input low. The
auto-zero loop is opened. The auto-zero capacitor is
placed in series in the loop to provide an equal and
opposite compensating offset voltage. The differential
voltage between input high and input low is integrated
for a fixed time of 2048 clock periods. At the end of this
phase, the polarity of the integrated signal is deter-
mined. If the input signal has no return to the con-
verter's power supply, input low can be tied to analog
common to establish the correct Common mode
voltage.
3.1.3
DE-INTEGRATE PHASE
Input high is connected across the previously charged
reference capacitor and input low is internally con-
nected to analog common. Circuitry within the chip
ensures the capacitor will be connected with the correct
polarity to cause the integrator output to return to the
zero crossing (established by auto-zero), with a fixed
slope. The time, represented by the number of clock
periods counted for the output to return to zero, is
proportional to the input signal.
30
BUFF
Buffer Amplifier Output.
31
AZ
Auto-Zero Node - Inside foil of CAZ.
32
INT
Integrator Output - Outside foil of CINT.
33
COMMON
Analog Common - System is auto-zeroed to COMMON.
34
IN LO
Differential Input Low Side.
35
IN HI
Differential Input High Side.
36
REF IN+
Differential Reference Input Positive.
37
REF CAP+
Reference Capacitor Positive.
38
REF CAP-
Reference Capacitor Negative.
39
REF IN-
Differential Reference Input Negative.
40
V+
Positive Supply Voltage - Nominally +5V with respect to GND (Pin 1).
TABLE 2-1:
PIN FUNCTION TABLE (CONTINUED)
Pin Number
(40-Pin PDIP)
Symbol
Description
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