參數(shù)資料
型號(hào)： TC655EUN
元件分類： 運(yùn)動(dòng)控制電子
英文描述： BRUSHLESS DC MOTOR CONTROLLER, PDSO10
封裝： PLASTIC, MSOP-10
文件頁(yè)數(shù)： 31/36頁(yè)
文件大小： 706K
代理商： TC655EUN
TC654/TC655
DS21734A-page 4
2002 Microchip Technology Inc.
TEMPERATURE SPECIFICATIONS
TIMING SPECIFICATIONS
2-Wire Serial Bus Interface
Logic Input High
VIH
2.1
—
V
Note 2
Logic Input Low
VIL
——
0.8
V
Logic Output Low
VOL
——
0.4
V
IOL = 3 mA
Input Capacitance SDA, SCLK
CIN
—10
15
pF
Note 1
I/O Leakage Current
ILEAK
-1.0
—
+1.0
A
SDA Output Low Current
IOLSDA
6—
—
mA
VOL = 0.6 V
Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 3.0 V to 5.5 V
Parameters
Symbol
Min
Typ
Max
Conditions
Temperature Ranges
Specified Temperature Range
TA
-40
—
+85
Operating Temperature Range
TA
-40
—
+125
Storage Temperature Range
TA
-65
—
+150
Thermal Package Resistances
Thermal Resistance, 10 Pin MSOP
θJA
—113
—
Electrical Characteristics: Unless otherwise noted, all limits are specified for VDD = 3.0 V to 5.5 V,
-40°C <TA < +85°C
Parameters
Sym
Min
Typ
Max
Units
Conditions
SMBus Interface (See Figure 1-1)
Serial Port Frequency
fSC
0
—
100
kHz
Low Clock Period
tLOW
4.7
—
sec Note 1
High Clock Period
tHIGH
4.7
—
sec Note 1
SCLK and SDA Rise Time
tR
—
1000
nsec Note 1
SCLK and SDA Fall Time
tF
—
300
nsec Note 1
Start Condition Setup Time
tSU(START)
4.7
—
sec Note 1
SCLK Clock Period Time
tSC
10
—
sec Note 1
Start Condition Hold Time
tH(START)
4.0
—
sec Note 1
Data in SetupTime to SCLK
High
tSU-DATA
250
—
nsec Note 1
Data in Hold Time after SCLK
Low
tH-DATA
300
—
nsec Note 1
Stop Condition Setup Time
tSU(STOP)
4.0
—
sec Note 1
Bus Free Time Prior to New
Transition
tIDLE
4.7
—
sec Note 1 and Note 2
Note 1: Not production tested, ensured by design, tested during characterization.
2: Time the bus must be free before a new transmission can start.
ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise noted, all limits are specified for VDD = 3.0 V to 5.5 V,
-40°C <TA < +85°C.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Note 1: Not production tested, ensured by design, tested during characterization.
2: For 5.0 V > VDD ≤ 5.5 V, the limit for VIH = 2.2 V.
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