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參數(shù)資料
| 型號： | TC6216M |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 16 Port 10/100 Unmanaged QoS Ethernet Switch |
| 中文描述： | 非網(wǎng)管16端口10/100以太網(wǎng)交換機(jī)的QoS |
| 文件頁數(shù)： | 12/28頁 |
| 文件大?。?/td> | 568K |
| 代理商： | TC6216M |
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TC6216M
- 12 -
Ver. 2.1
5/24/01
7
Ethernet Media Access Controller
The Ethernet Media Access Controller (MAC) contains IEEE 802.3 MAC functions for 16 ports. It is able to
operate in 10/100 speed modes, full and half duplex. Each port has its dedicated receive and transmit FIFO
′
s
with necessary logic to implement flow-control for both duplex modes. The MAC functions are optimized and
tailored for high speed and flexible interfacing.
7.1
Receive MAC
When a frame is received from the Ethernet media through the RMII, the data is stored in a receive FIFO. The
FIFO acts as a temporary buffer between the Receive MAC section and switch core interface.
The Receive MAC layer decomposes Ethernet packets acquired from the PHY layer via RMII, by stripping off
the preamble sequence and SFD. The Receive MAC then sends packets to the receive FIFO along with packet
validity information.
The MAC determines the validity of each received packet by checking the CRC and packet length. The bad
packets will be dropped either by the MAC or by the queue manager. Oversized packets are truncated to 1536
bytes and marked to be erroneous.
Undersized packets are removed from the receive FIFO without being
reported at the switch interface. The FIFO space held by undersized packets is automatically recovered by
removing the packet.
The Receive MAC is also able to reject Mac Control Type frames (type 88-08). To activate this filtering function
it must be selected using
RejMCT
pin or the equivalent EEPROM bit.
When the TC6216M receives a MAC control frame and determines that the opcode is a PAUSE command (flow
control frame) and the frame
′
s CRC is OK, the chip will load its internal pause counter with the
′
time value
′
variable extracted from the incoming flow control packet. If the pause counter is not
′
zero
′
the Receive MAC will
XOFF the Transmit MAC. The pause counter will decrement after each slot time and will XON the Transmit
MAC when the
′
zero
′
value is reached.
If a frame transmission is in progress when the PAUSE frame is received, the transmission is allowed to
complete but it will be stopped for the next packets until an XON command is generated by the Receive MAC.
The pause time will begin at the end of current transmission or immediately (if no transmission is in course at the
moment of receiving the PAUSE frame). If a pause command is received while the transmitter is already in
pause, the new pause time indicated by the new Flow Control frame will be loaded into the pause register.
When the receive FIFO is full and additional data are still incoming from the MAC, then the overrun condition
occurs and the frame is dropped. If the system clock frequency is not lower than the recommended value this
condition will not occur.
Transmit MAC
7.2
The Transmit MAC section assembles the MAC frames stored in the transmit FIFO and controls their
transmission onto the media via external PHY entities. It appends the standard preamble and start of frame
delimiter to the transmitted packets. The Transmit MAC also controls the InterFrameGap time during
transmission, maintaining for default the standard minimum InterFrameGap of 96 bit time. This value can be
changed by EEPROM setting.
For half duplex mode the Transmit MAC meets CSMA/CD IEEE 802.3
requirements. The FIFO logic manages
frame retransmission for early collision conditions or discards the frame if late collision occurs. It also follows
the truncated binary exponential backoff algorithm, collision and jamming procedures.
The transmit FIFO buffers the packets available for transmission in the main memory queues.
If the transmit
FIFO gets empty before the packet currently in transmission reaches its end, an underrun condition is generated.
When the switch core transfers the rest of the packet into the FIFO the Transmit MAC safely discards it without
affecting the next packet. Underrun conditions will not occur if the system is operated at the recommended clock
frequency or higher.
For full duplex mode the TC6216M implements the flow-control algorithm according with the IEEE 802.3x
standard.
The chip uses the XON/XOFF method adjusting the Pause Value field inside the MAC Pause Frame
according to traffic conditions. The full duplex flow control can be enabled/disabled depending on
autonegotiation result, pin configuration and/or EEPROM settings.
The TC6216M executes backpressure algorithm as half duplex flow control mode if not disabled by
DisBPr
pin
or EEPROM
(ConfigRegPx[1])
. The backpressure algorithm is based on carrier sense forced collisions and an
aggressive backoff algorithm. The forced consecutive collisions generated for flow control purposes can be
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