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參數(shù)資料
| 型號： | TC3827-4.2VUA |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | Lithium-Ion Battery Charger |
| 中文描述： | 鋰離子電池充電器 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大小： | 143K |
| 代理商： | TC3827-4.2VUA |
6
Lithium-Ion Battery Charger
TC3827
Lower Current Option
TC3827-2 12/12/00
2001 Microchip Technology Inc. DS21558A
Preregulated Input Voltage (5V +/- 10%)
If lower charging current is allowed, the
Θ
JA
value can be
increased, and the system cost decreased. This is accom-
plished by using a FDC638P PMOS, for example, in a 6-Pin
SOT package mounted on a small 1in x 1in area of 2oz Cu
on FR-4 board. This provides a convection cooled thermal
impedance of
Θ
JA
= +78
°
C/W. Allowing a maximum FET
junction temperature of +150
°
C, at +50
°
C ambient, with
convection cooling the maximum allowed heat rise is:
150
°
C–50
°
C = 100
°
C.
The maximum short circuit current, I
SC,
is found as:
I
SC
=
T/(
Θ
JA
x V
IN
) = 100/(78 x 5.5) = 0.23A
Thus the maximum charging current, I
MAX
, is:
I
MAX
= I
SC
/k = 0.51A
The current sense resistor for this application is then:
R
SENSE
= V
CS
/I
MAX
= 0.05/0.51 = 98m
≈
100m
FET Selection
The type and size of the pass transistor is determined by
the threshold voltage, input-output voltage differential and
load current. The selected PMOS must satisfy the physical
and thermal design requirements. To ensure that the maxi-
mum V
GS
provided by the controller will turn on the FET at
worst case conditions, (i.e., temperature and manufacturing
tolerances) the maximum available V
GS
must be deter-
mined. Maximum V
GS
is calculated as follows:
V
GSMAX
= V
IN
– (I
MAX
x R
SENSE
)
– V
DRVMAX
For example:
V
IN
= 5V, and I
MAX
= 1A,
V
GSMAX
= 5V - (1A x 50m
)
– 1V= 3.95V
The difference between V
IN
and V
O
(V
DS
) must exceed
the voltage drop due to the sense resistor plus the ON-
resistance of the PMOS at the maximum charge current.
V
DS
≤
V
IN
– V
O
– V
CS
= 5V – 4.2V – 0.075V = 0.725V
The maximum R
DS(ON)
required at the available gate drive
(V
DR
) and Drain-to-Source voltage (V
DS
) is:
R
DS(ON)
= V
DS
/I
MAX
≤
0.725V/1A = 725m
The selected PMOS must satisfy these criteria.
External Capacitors
The TC3827 is stable with or without a battery load, and
virtually any good quality output filter capacitors can be
used, independent of the capacitor’s minimum ESR (Effec-
tive Series Resistance) value. The actual value of the
capacitor and its associated ESR depends on the g
m
and
capacitance of the external PMOS device. A 22
μ
F tantalum
or aluminum electrolytic capacitor at the output is sufficient
to ensure stability for up to a 10A output current.
Shutdown Mode
Applying a logic high signal to the SHDN
pin or tying it
to the input pin will enable the output. Pulling this pin low or
tying it to ground will disable the output. In shutdown mode,
the controller’s quiescent current is reduced to typically 1
μ
A.
Short Circuit Protection
The PMOS is protected during short circuit conditions
with a foldback type of current limiting that reduces the
power dissipation.
Current Sense Resistor
The current limit sense resistor, R
SENSE
, is calculated
previously. Proper de-rating is advised to select the power
dissipation rating of the resistor. The simplest and cheapest
sense resistor for high current applications, is a PCB trace.
However, the temperature dependence of the copper trace
and the thickness tolerances of the trace must be consid-
ered in the design.
Copper’s Tempco, in conjunction with the proportional-
to-absolute temperature (
±
0.3%) current limit voltage, can
provide an accurate current limit. Alternately, an appropriate
sense resistor, such as surface mount sense resistors,
available from KRL, can be used.
PCB Layout Issues
For optimum voltage regulation, place the load as close
as possible to the device’s V
OUT
and GND pins. It is
recommended to use dedicated PCB traces to connect the
PMOS drain to the positive terminal and V
SS
to the negative
terminal of the load to avoid voltage drops along the high
current carrying PCB traces.
If the PCB layout is used as a heatsink, adding many
vias around the power FET helps conduct more heat from
the FET to the back-plane of the PCB, thus reducing the
maximum FET junction temperature.
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