
MPEG-4 Audiovisual Codec LSI
Preliminary
TC35273
TOSHIBA Confidential
2000-4-27
6/23
Version 0.90
Table 1. System Control Signals
Signal Name
In/Out
Bit Width
Description
/RESET
In
1
System Reset Input (Low Active). When the LSI is reset, the reset pin has
to be low for more than 16 clock cycles. When power on, the LSI has to be
reset after PLL locked. It takes approximately 100us until the PLL locked.
STANDBY
In
1
System Standby Input (High Active).
When it is high, power is not supplied to the internal logic, SRAM, and
DRAM.
“0”: Normal Operation.
“1”: Standby.
Table 2. PLL Control Signals
Signal Name
In/Out
Bit Width
Description
PLLFN
In
1
Reference Clock Input.
It has to be 13.00MHz to 20MHz with +/- 10% duty.
PLLDIV[2:0]
In
3
System clock frequency select. System Clock = PLLFN * N.
“000”: N=2.5.
“001”: N=3.0.
“010” : N=3.5
“011”: N=4.0.
“100”: N=4.5.
“101”: N=5:0.
“110”: N=5.5.
“111”: N=6.0.
PLLAVD
In
1
Analog PLL Power (VDD).
PLLAVS
In
1
Analog PLL Ground (VSS).
Table 3. Host Interface
Signal Name
In/Out
Bit Width
Description
/HCS
In
1
Chip enable input (low active).
“0” : Chip select.
“1” : Non operation.
/HWR
In
1
Write strobe (low active).
“0” : Write operation.
“1” : Non operation.
/HRD
In
1
Read Strobe (low active).
“0” : Read operation.
“1” : Non operation.
HADDR[6:0]
In
7
Address signal.
HDAT[15:0]
In/Out
16
Data signal.
HWAIT
Out
1
Bus wait signal (low active).
“0” : Wait.
“1” : Non wait.
HINT
Out
1
Interrupt signal (high active).
“0” : Non operation.
“1” : Interrupt operation.
Table 4 Video General Serial Interface
Signal Name
In/Out
Bit Width
Description
VGSCLK
Out
1
General I/F clock output. Please open unless this interface is used.
VGSADIO
In/Out
1
Input/output of serial data on port A. Open unless this interface is used.
VGSBDO
Out
1
Output of serial data on port B. Open unless this interface is used.