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參數(shù)資料
| 型號： | TC3405 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 16-Bit, Low Cost, Low Power Sigma-Delta A/D Converter |
| 中文描述： | 16位，低成本，低功耗Σ-ΔA / D轉(zhuǎn)換 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 453K |
| 代理商： | TC3405 |
TC3405
DS21414B-page 6
2002 Microchip Technology Inc.
3.0
DETAILED DESCRIPTION
The TC3405 has a 16-bit sigma-delta A/D converter. It
has one differential input, three single-ended inputs, an
analog multiplexer and a V
DD
monitor with reset gener-
ator. See the Typical Application circuit and the
Functional Block diagram. The key components of the
TC3405 are described below.
Also refer to Figure 3-5, A/D Operational Flowchart and
the Timing Diagrams, Figure 3-1, Figure 3-2 and
Figure 3-3.
3.1
A/D Converter Operation
When the TC3405 is not converting, it is in Sleep mode
with both the SCLK and SDAT lines high. An A/D
conversion is initiated by a high to low transition on the
SCLK line at which time the internal clock of the
TC3405 is started and the address value (A0 and A1)
is internally latched. The address value steers the ana-
log multiplexer to select the input channel to be
converted. Each additional high to low transition of
SCLK (following the initial SCLK falling edge) during
the time interval t
4,
will decrement the conversion
resolution by one bit and reduce the conversion time by
one half. The time interval t
4
is referred to as the
resolution reduction window. The minimum conversion
resolution is 10-bits so any more than 6 SCLK
transitions during t
4
will be ignored.
After each high to low transition of SCLK, in the t
4
interval, the SDAT output is driven high by the TC3405
to acknowledge that the resolution has been decre-
mented. When the SCLK returns high or the t
4
interval
ends, the SDAT line returns low (see Figure 3-2). When
the conversion is complete SDAT is driven high. The
TC3405 now enters Sleep mode and the conversion
value can be read as a serial data word on the SDAT
line.
3.2
Reading the Data Word
After the conversion is complete and SDAT goes high,
the conversion value can be clocked serially onto the
SDAT line by high to low transitions of the SCLK. The
data word is in two’s compliment format with the sign bit
clocked onto the SDAT line, first followed by the MSB
and ending in the LSB. For a 16-bit conversion the data
word would consist of a sign bit followed by 15 magni-
tude bits, Table 3-1 shows the data word versus input
voltage for a 16-bit conversion. Note that the full scale
input voltage range is ±(2 REF
IN
– 1LSB). When
REF
OUT
is fed back directly to REF
IN
, an LSB is 73
μ
V
for a 16-bit conversion, as REF
OUT
is typically 1.193V.
Figure 3-4 shows typical SCLK and SDAT waveforms
for 16, 12 and 10-bit conversions. Note that any com-
plete convert and read cycle requires 17 negative edge
clock pulses. The first is the convert command. Then,
up to six of these can occur in the resolution reduction
window, t
4
, to decrement resolution. The remaining
pulses clock out the conversion data word.
TABLE 3-1:
DATA CONVERSION WORD
VS. VOLTAGE INPUT
(REF
IN
= 1.193V)
The SCLK input has a filter which rejects any positive
or negative pulse of width less than 50nsec to reduce
noise. The rejection width of this pulse can vary
between 50nsec and 750nsec depending on process-
ing parameters and supply voltage.
Figure 3-1 and Table 3-2 show information for deter-
mining the mode of operation for the TC3401 part by
recording the value of SDAT for SCLK in a high, then
low, then high state. For example, if SCLK goes
through a 1-0-1 transition and the corresponding
values of SDAT are 1-1-0, then the SCLK falling edge
started a new data conversion. A 0-1-0 for SDAT would
have indicated a resolution reduction had occurred.
This is useful if the microcontroller has a Watchdog
Reset or otherwise loses track of where the TC3405 is
in the conversion and data readout sequence. The
microcontroller can simply transition SCLK until it
“finds” a Start Conversion condition.
FIGURE 3-1:
SCLK, SDAT LOGIC
STATE DIAGRAM
TABLE 3-2:
SCLK, SDAT LOGIC STATE
*
Note:
The code X00 has a dual meaning: Data Transfer or
Busy converting. To avoid confusion, the user should
send only the required number of pulses for the
desired resolution, then wait for SDAT to rise to 1,
indicating conversion is complete before clocking
SCLK again to read out data bits.
Data Word
INn
+
– INn- (Volts)
0111 1111 1111 1111
2.38596 (Positive Full Scale)
72.8 E -6
0
-72.8 E -6
-2.38596 (Negative Full Scale)
Reserved Code
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1000 0000 0000 0001
1000 0000 0000 0000
A
B
C
Status
1
0
x
x
1
1
1
0
0
0
1
0
Start Conversion
Resolution Reduction
Data Transfer
Data Transfer or Busy*
SCLK
SDAT
A
B
C
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