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參數(shù)資料
| 型號(hào)： | TC33163EOETR |
| 元件分類(lèi)： | 穩(wěn)壓器 |
| 英文描述： | 3.4 A SWITCHING CONTROLLER, 55 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁(yè)數(shù)： | 13/17頁(yè) |
| 文件大小： | 225K |
| 代理商： | TC33163EOETR |
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5
TC33163
TC33163-1 5/16/00
Power Switching Regulators
INTRODUCTION
The TC33163 series are monolithic power switching
regulators optimized for DC-to-DC converter applica-
tions. The combination of features in this series enables
the system designer to directly implement step-up, step-
down, and voltage-inverting converters with a minimum
number of external components. Potential applications
include cost sensitive consumer products as well as
equipment for the automotive, computer, and industrial
markets. A Representative Block Diagram is shown in
Figure 1.
OPERATING DESCRIPTION
The TC33163 operates as a fixed on-time, variable
off-time voltage mode ripple regulator. In general, this
mode of operation is somewhat analogous to a capacitor
charge pump and does not require dominant pole loop
compensation for converter stability. The Typical Operat-
ing Waveforms are shown in Figure 2. The output voltage
waveform shown is for a step-down converter with the
ripple and phasing exaggerated for clarity. During initial
converter startup, the feedback comparator senses that
the output voltage level is below nominal. This causes the
output switch to turn on and off at a frequency and duty
cycle controlled by the oscillator, thus pumping up the
output filter capacitor. When the output voltage level
reaches nominal, the feedback comparator sets the latch,
immediately terminating switch conduction. The feed-
back comparator will inhibit the switch until the load
current causes the output voltage to fall below nominal.
Under these conditions, output switch conduction can be
inhibited for a partial oscillator cycle, a partial cycle plus a
complete cycle, multiple cycles, or a partial cycle plus
multiple cycles.
Oscillator
The oscillator frequency and on-time of the output
switch are programmed by the value selected for timing
capacitor CT. Capacitor CT is charged and discharged by
a 9 to 1 ratio internal current source and sink, generating
a negative going sawtooth waveform at Pin 6. As CT
charges, an internal pulse is generated at the oscillator
output. This pulse is connected to the NOR gate center
input, preventing output switch conduction, and to the
AND gate upper input, allowing the latch to be reset if the
comparator output is low. Thus, the output switch is
always disabled during ramp-up and can be enabled by
the comparator output only at the start of ramp-down. The
oscillator peak and valley thresholds are 1.25V and 0.55V,
respectively, with a charge current of 225
A and a dis-
charge current of 25
A, yielding a maximum on-time duty
cycle of 90%. A reduction of the maximum duty cycle may
This can be accomplished with the addition of an external
deadtime resistor (RDT) placed across CT. The resistor in-
creases the discharge current which reduces the on-time of
the output switch. A graph of the Output Switch On-Off Time
versus Oscillator Timing Capacitance for various values of
RDT is shown in Figure 11. Note that the maximum output duty
cycle, (tON/tON + tOFF), remains constant for values of CT
greater than 0.2nF. The converter output can be inhibited by
clamping CT to ground with an external NPN small-signal
transistor.
Feedback and Low Voltage Indicator Comparators
Output voltage control is established by the Feedback
comparator. The inverting input is internally biased at
1.25V and is not pinned out. The converter output voltage is
typically divided down with two external resistors and moni-
tored by the high impedance noninverting input at Pin 2. The
maximum input bias current is
±0.4A, which can cause an
output voltage error that is equal to the product of the input bias
current and the upper divider resistance value. For applica-
tions that require 5.0V, the converter output can be directly
connected to the noninverting input at Pin 3. The high imped-
ance input, Pin 2, must be grounded to prevent noise pickup.
The internal resistor divider is set for a nominal voltage of
5.05V. The additional 50mV compensates for a 1.0% voltage
drop in the cable and connector from the converter output to
the load. The Feedback comparator’s output state is con-
trolled by the highest voltage applied to either of the two
noninverting inputs.
The Low Voltage Indicator (LVI) comparator is designed
for use as a reset controller in microprocessor-based
systems. The inverting input is internally biased at 1.125V,
which sets the noninverting input thresholds to 90% of nomi-
nal. The LVI comparator has 15mV of hysteresis to prevent
erratic reset operation. The Open Collector output is capable
of sinking in excess of 6.0mA (see Figure 20). An external
resistor (RLVI ) and capacitor (CDLY ) can be used to program
a reset delay time (tDLY ) by the formula shown below, where
VTH(MPU) is the microprocessor reset input threshold. Refer to
Figure 3.
Current Limit Comparator,Latch and Thermal Shutdown
With a voltage mode ripple converter operating under
normal conditions, output switch conduction is initiated by the
oscillator and terminated by the Voltage Feedback compara-
tor. Abnormal operating conditions occur when the converter
output is overloaded or when feedback voltage sensing is lost.
Under these conditions, the Current Limit comparator will
protect the Output Switch.
1 –
(
VOUT
VTH (MPU)
1
tDLY = RLVI CDLY In
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