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| 型號(hào)： | TC32MCDBTR |
| 元件分類(lèi)： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO4 |
| 封裝： | SOT-223, 3 PIN |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大?。?/td> | 242K |
| 代理商： | TC32MCDBTR |
2006 Microchip Technology Inc.
DS21402C-page 5
TC32M
3.0
DETAILED DESCRIPTION
The TC32M provides three important functions to
safeguard stable processor operation: precision pro-
cessor monitor, Watchdog sanity timer and external
override Reset control.
3.1
Processor Monitor
The RS pin is immediately driven low any time VDD is
below the nominal threshold voltage. As a result, this
pin is LOW when power is initially applied, holding the
processor in its Reset state. RS remains low for a
minimum of 500 msec after VDD is within tolerance to
allow the power supply and processor to stabilize.
3.2
Watchdog Timer
The processor drives the RS pin with an input/output
(I/O) line in series with an resistor voltage divider to
VDD. Pulling the bottom resistor of this divider low
results in an internal voltage change (strobe) sufficient
to reset the Watchdog Timer, but above the VIL input
threshold of the processor Reset pin. The processor
must continuously apply strobes in this manner within
a set period to verify proper software execution. A
momentary Reset (500 msec minimum) is generated
by the TC32M if a hardware or software failure keeps
RS from being strobed within the Watchdog Time-out
period. This action typically initiates the processor’s
power-up routine. If the interruption persists, new
Reset pulses are generated each time-out period until
RS is strobed. This time-out period is typically 700
msec.
FIGURE 3-1:
Watchdog Strobe
The software routine that drives the RS strobe must be
in a section of the program that executes frequently
enough so the time between toggles is less than one
Watchdog Time-out period. The strobe signal can be
derived from microprocessor address, data and/or
control signals. Typical circuit examples are shown in
Figure .
3.3
Resistor Value Selection
The values of R1 and R2 must be chosen to ensure a
valid low strobe level (VSTL) on RS when the processor
I/O line is low. The use of 10 k
Ω, ±5% tolerance
resistors are recommended. These values result in a
nominal strobe level of 2.5 on RS (min/max of 2.13V/
3.08V, assuming VDD = 5.0V ±10%). Other resistor
values can be used, so long as the additive tolerances
of the power supply and resistor values result in a
strobe that falls within VSTH and VSTL under all additive
tolerance conditions.
VSTL (Max)
tST
tTD
RS
Note: tTD is the maximum elapsed time between strobes which
will keep the watchdog timer from forcing RS LOW.
(A Strobe is defined as a high-to-low transition from VSTH to VSTL).
VSTH (Min)
VSTL (Min)
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