參數(shù)資料
型號(hào): TC14433COG
廠商: TelCom Semiconductor, Inc.
元件分類: 串行ADC
英文描述: 3-1/2 DIGIT A/D CONVERTERS
中文描述: 3-1/2位數(shù)的A / D轉(zhuǎn)換器
文件頁數(shù): 4/10頁
文件大?。?/td> 149K
代理商: TC14433COG
3-130
TELCOM SEMICONDUCTOR, INC.
3-1/2 DIGIT A/D CONVERTERS
TC14433
TC14433A
PIN DESCRIPTIONS
Pin No.
24-Pin
PDIP/CerDip
1
Pin No.
24-Pin
SOIC
1
Pin No.
28-Pin
PLCC
2
Symbol
V
AG
Description
This is the analog ground; it has a high input impedance — This pin
determines the reference level for the unknown input voltage (V
X
) and the
reference voltage (V
REF
).
2
2
3
V
REF
Reference voltage — Full-scale output is equal to the voltage applied to
V
REF
. Therefore, full-scale voltage of 1.999V requires 2V reference and
199.9 mV full-scale requires a 200 mV reference. V
REF
functions as system
reset also. When switched to V
EE
, the system is reset to the beginning of
the conversion cycle.
3
3
4
V
X
The unknown input voltage (V
X
) is measured as a ratio of the reference
voltage (V
REF
) in a ratiometric A/D conversion.
4
4
5
R
1
These pins are for external components used for the integration function in
the dual slope conversion. Typical values are 0.1
μ
F (mylar) capacitor for C
1
.
R
1
= 470 kW (resistor) for 2V full-scale.
5
5
6
R
1
/C
1
6
6
7
C
1
R
1
= 27 kW (resistor) for 200 mV full-scale. Clock frequency of 66 kHz gives
250 msec conversion time. See equation below for calculation of integrator
component values.
7
8
7
8
9
CO
1
CO
2
These pins are used for connecting the offset correction capacitor. The
recommended value is 0.1
μ
F.
10
9
9
11
DU
Display update input pin — When DU is connected to the EOC output every
conversion is displayed. New data will be strobed into the output latches
during the conversion cycle if a positive edge is received on DU prior to the
ramp-down cycle. When this pin is driven from an external source, the
voltage should be referenced to V
SS
.
10
10
12
CLK
1
Clock input pins — The TC14433 has its own oscillator system clock.
Connecting a single resistor between CLK
1
and CLK
0
sets the clock frequency.
11
11
13
CLK
0
A crystal or OC circuit may be inserted in lieu of a resistor for improved
CLK
1
, the clock input, can be driven from an external clock source,
which need only have standard CMOS output drive. This pin is referenced to
V
EE
for external clock inputs. A 300 kW resistor yields a clock frequency of
about 66 kHz. (See typical characteristic curves; see Figure 9 for alternate
circuits.)
12
12
14
V
EE
Negative power current — Connection pin for the most negative supply. Please
note the current for the output drive circuit is returned through V
SS
. Typical
supply current is 0.8 mA.
13
13
16
V
SS
Negative power supply for output circuitry — This pin sets the low voltage level
for the output pins (BCD, Digit Selects, EOC, OR). When connected to analog
ground, the output voltage is from analog ground to V
DD
. If connected to V
EE
,
the output swing is from V
EE
to V
DD
. The recommended operating range for
V
SS
is between the V
DD
–3 volts and V
EE
.
14
14
17
EOC
End of conversion output generates a pulse at the end of each conversion
cycle. This generated pulse width is equal to one-half the period of the system
clock.
15
15
18
OR
Overrange pin — Normally this pin is set high. When V
X
exceeds V
REF
the OR
pin is low.
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