參數(shù)資料
型號: TC14433AELITR
元件分類: ADC
英文描述: 1-CH 3-BIT DUAL-SLOPE ADC, SERIAL ACCESS, PQCC28
封裝: PLASTIC, LCC-28
文件頁數(shù): 21/24頁
文件大小: 382K
代理商: TC14433AELITR
TC14433/A
DS21394D-page 6
2008 Microchip Technology Inc.
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
Pin No.
24-Pin PDIP,
SOIC
Pin No.
28-Pin
PLCC
Symbol
Description
12
VAG
This is the analog ground. It has a high input impedance. The pin determines
the reference level for the unknown input voltage (VX) and the reference
voltage (VREF).
23
VREF
Reference voltage – Full scale output is equal to the voltage applied to VREF.
Therefore, full scale voltage of 1.999V requires 2V reference and 199.9 mV
full scale requires a 200 mV reference. VREF functions as system reset also.
When switched to VEE, the system is reset to the beginning of the
conversion cycle.
34
VX
The unknown input voltage (VX) is measured as a ratio of the reference
voltage (VREF) in a ratiometric A/D conversion.
45
R1
This pin is for external components used for the integration function in the
dual slope conversion. Typical values are 0.1 F (Mylar) capacitor for C1.
56
R1/C1
R1 = 470 kΩ (resistor) for 2V full scale.
67
C1
R1 = 27 kΩ (resistor) for 200 mV full scale. Clock frequency of 66 kHz gives
250 ms conversion time.
79
CO1
These pins are used for connecting the offset correction capacitor. The
recommended value is 0.1 F.
810
CO2
These pins are used for connecting the offset correction capacitor. The
recommended value is 0.1 F.
9
11
DU
Display update input pin. When DU is connected to the EOC output, every
conversion is displayed. New data will be strobed into the output latches
during the conversion cycle if a positive edge is received on DU, prior to the
ramp down cycle. When this pin is driven from an external source, the
voltage should be referenced to VSS.
10
12
CLK1
Clock input pins. The TC14433 has its own oscillator system clock.
Connecting a single resistor between CLK1 and CLK0 sets the clock
frequency.
11
13
CLK0
A crystal or OC circuit may be inserted in lieu of a resistor for improved
CLK1, the clock input, can be driven from an external clock source, which
need only have standard CMOS output drive. This pin is referenced to VEE
for external clock inputs. A 300 k
Ω resistor yields a clock frequency of about
Figure 5-3 for alternate circuits.)
12
14
VEE
Negative power current. Connection pin for the most negative supply. Please
note the current for the output drive circuit is returned through VSS. Typical
supply current is 0.8 mA.
13
16
VSS
Negative power supply for output circuitry. This pin sets the low voltage level
for the output pins (BCD, Digit Selects, EOC, OR). When connected to
analog ground, the output voltage is from analog ground to VDD. If
connected to VEE, the output swing is from VEE to VDD. The recommended
operating range for VSS is between the VDD -3 volts and VEE.
14
17
EOC
End of conversion output generates a pulse at the end of each conversion
cycle. This generated pulse width is equal to one half the period of the
system clock.
15
18
OR
Overrange pin. Normally this pin is set high. When VX exceeds VREF the OR
is low.
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