參數(shù)資料
型號： TC1322EOA
廠商： Microchip Technology Inc.
英文描述： 12-Bit Digital-to-Analog Converter with Two-Wire Interface
中文描述： 12位數(shù)字到模擬轉(zhuǎn)換器兩線接口
文件頁數(shù)： 3/16頁
文件大小： 445K
代理商： TC1322EOA
2002 Microchip Technology Inc.
DS21388B-page 3
TC1322
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings*
Supply Voltage (V
DD
).............................................+6V
Voltage on any Pin....(GND – 0.3V) to (V
DD
+ 0.3V)
Current on any Pin............................................±50mA
Package Thermal Resistance (
θ
JA
)............ 330°C C/W
Operating Temperature (T
A
)........................See Below
Storage Temperature (T
STG
)..............-65°C to +150°C
*Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress ratings only and functional operation of the device
at these or any other conditions above those indicated in the
operation sections of the specifications is not implied.
Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability.
TC1322 ELECTRICAL SPECIFICATIONS
Electrical Characteristics:
V
DD
= 2.7V to 5.5V, -40°C
≤
T
A
≤
+85°C, V
REF
= 1.2V, C
L
= 80pF, unless otherwise noted.
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
Power Supply
V
DD
I
DD
Supply Voltage
Operating Current
2.7
—
—
0.35
5.5
0.5
—
mA
V
DD
= 5.5V, V
REF
= 1.2V
Serial Port Inactive
(Note 1)
V
DD
= 3.3V
Serial Port Inactive
(Note 1)
I
DD-STANDBY
Standby Supply Current
—
0.1
1
μ
A
Static Performance - Analog Section
Resolution
Integral Non-Linearity at FS, T
A
= +25°C
Full Scale Error
Differential Non-Linearity, T
A
= +25°C
Offset Error at V
OUT
Offset Error Tempco at V
OUT
Power Supply Rejection Ratio
Voltage Reference Range
Reference Input Leakage Current
Voltage Swing
Output Resistance @ V
OUT
Output Current (Source or Sink)
Output Short-Circuit Current
V
DD
= 5.5V
Dynamic Performance
SR
Voltage Output Slew Rate
t
SETTLE
Output Voltage Full Scale Settling Time
t
WU
Wake-up Time
Digital Feed through and Crosstalk
Serial Port Interface
V
IH
Logic Input High
V
IL
Logic Input Low
V
OL
SDA Output Low
—
—
—
—
—
—
—
0
—
0
—
—
—
—
—
—
—
—
±0.3
10
80
—
—
—
5.0
2
30
20
10
±16
±3
+4
±8
—
—
Bits
LSB
%FS
LSB
mV
μ
v/°C
dB
V
μ
A
V
mA
mA
mA
INL
FSE
DNL
V
OS
TCV
OS
PSRR
V
REF
I
REF
V
SW
R
OUT
I
OUT
I
SC
(Note 2)
All Codes
(Note 2)
(Note 2)
V
DD
at DC
V
DD
– 1.2
±1.0
V
REF
—
—
50
50
V
REF
≤
(V
DD
– 1.2V)
R
OUT
(
)
Source
Sink
—
—
—
—
0.8
10
20
5
—
—
—
—
V/
μ
s
μ
sec
μ
s
nV-s
SDA = V
DD
, SCL = 100kHz
2.4
—
—
—
—
—
—
—
—
—
5
—
V
DD
0.6
0.4
0.6
0.4
±1.0
V
—
V
V
pF
μ
A
I
OL
= 3mA (Sinking Current)
I
OL
= 6mA
C
IN
I
LEAK
Note
Input Capacitance SDA, SCL
I/O Leakage
SDA and SCL must be connected to V
DD
or GND.
Measured at V
OUT
≥
50mV referred to GND to avoid output buffer clipping.
1:
2:
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