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參數(shù)資料
| 型號(hào)： | TC1271SERC |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 4-Pin レP Reset Monitors |
| 中文描述： | 4引腳レP復(fù)位監(jiān)控器 |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大?。?/td> | 467K |
| 代理商： | TC1271SERC |
2002 Microchip Technology Inc.
DS21381B-page 5
TC1270/TC1271
3.0
APPLICATIONS INFORMATION
3.1
V
CC
Transient Rejection
The TC1270/TC1271 provides accurate V
CC
monitor-
ing and reset timing during power-up, power-down, and
brownout/sag conditions, and rejects negative-going
transients (glitches) on the power supply line. Figure
3-1
shows the
maximum transient
maximum negative excursion (overdrive) for glitch
rejection. Any combination of duration and overdrive
that lays
under
the curve will
not
generate a reset
signal. Combinations above the curve are detected as
a brownout or power-down. Transient immunity can be
improved by adding a capacitor in close proximity to the
V
CC
pin of the TC1270/TC1271.
duration
vs.
FIGURE 3-1:
MAXIMUM TRANSIENT
DURATION VS.
OVERDRIVE FOR GLITCH
REJECTION AT 25°C
3.2
RESET Signal Integrity During
Power-Down
The TC1270 RESET output is valid to V
CC
= 1.0V.
Below this voltage the output becomes an "open
circuit" and does not sink current. This means CMOS
logic
inputs
to
the
μ
P
undetermined
voltage.
Most
completely
shut
down
well
However,
in
situations
where
maintained valid to V
CC
= 0V, a pull-down resistor must
will
be
digital
above
RESET
floating
systems
this
at
an
are
voltage.
must
be
be connected from RESET to ground to discharge stray
capacitances and hold the output low (Figure 3-2). This
resistor value, though not critical, should be chosen
such that it does not appreciably load RESET under
normal operation (100k
will be suitable for most
applications). Similarly, a pull-up resistor to V
CC
is
required for the TC1271 to ensure a valid high RESET
for V
CC
below 1.1V.
FIGURE 3-2:
ENSURING RESET VALID
TO V
CC
= 0V
3.3
Processors With Bidirectional
I/O Pins
Some
μ
P's (such as Motorola 68HC11) have bi-
directional reset pins. Depending on the current drive
capability of the processor pin, an indeterminate logic
level may result if there is a logic conflict. This can be
avoided by adding a 4.7 k
resistor in series with the
output of the TC1270/TC1271 (Figure 3-3). If there are
other components in the system which require a reset
signal, they should be buffered so as not to load the
reset line. If the other components are required to
follow the reset I/O of the
μ
P, the buffer should be
connected as shown with the solid line.
FIGURE 3-3:
INTERFACING TO
BIDIRECTIONAL
RESET I/O
RESET COMPARATOR OVERDRIVE,
V
TH
- V
CC
(mV)
400
240
160
320
80
0
1
10
100
1000
M
μ
s
T
A
°
C
V
TH
Duration
Overdrive
V
CC
TC127LMJ
TC127xR/S/T
TC1270
V
CC
V
CC
R1
100k
RESET
GND
TC1270
V
CC
RESET
GND
RESET
GND
Buffered RESET
To Other System
Components
Buffer
μ
P
4.7k
V
CC
V
CC
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TC1271SERCTR | 功能描述:監(jiān)控電路 4-Pin uP 2.93V Reset RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過(guò)電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| TC1271TERC | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:4-Pin レP Reset Monitors |
| TC1271TERCTR | 功能描述:監(jiān)控電路 4-Pin uP 38V Reset RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過(guò)電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| TC1272 | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:3-Pin Reset Monitors for 5V Systems |
| TC1272-10ENBTR | 功能描述:監(jiān)控電路 3-Pin for 5V Systems RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過(guò)電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
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