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參數(shù)資料
| 型號(hào)： | TC1185-2.6VCT713 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 50 mA, 100 mA and 150 mA CMOS LDOs with Shutdown and Reference Bypass |
| 中文描述： | 50毫安，100 mA和一百五毫安的CMOS關(guān)機(jī)和參考繞道低壓降穩(wěn)壓器 |
| 文件頁(yè)數(shù)： | 11/22頁(yè) |
| 文件大?。?/td> | 618K |
| 代理商： | TC1185-2.6VCT713 |
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2007 Microchip Technology Inc.
DS21335E-page 11
TC1014/TC1015/TC1185
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in
Table 3-1
.
TABLE 3-1:
PIN FUNCTION TABLE
3.1
Input Voltage (V
IN
)
Connect the V
IN
pin to the unregulated source
voltage. Like all low dropout linear regulators, low
source impedance is necessary for the stable
operation of the LDO. The amount of capacitance
required to ensure low source impedance will
depend on the proximity of the input source
capacitors or battery type. For most applications,
1.0 μF of capacitance will ensure stable operation
of the LDO circuit. The type of capacitor used can
be ceramic, tantalum or aluminum electrolytic.
The low Effective Series Resistance (ESR) char-
acteristics of the ceramic will yield better noise
and Power Supply Ripple Rejection (PSRR)
performance at high frequency.
3.2
Ground Terminal (GND)
Connect the ground pin to the input voltage
return. For the optimal noise and PSRR
performance, the GND pin of the LDO should be
tied to a quiet circuit ground. For applications
have switching or noisy inputs tie the GND pin to
the return of the output capacitor. Ground planes
help lower inductance and voltage spikes caused
by fast transient load currents and are
recommended for applications that are subjected
to fast load transients.
3.3
Shutdown (SHDN)
The Shutdown input is used to turn the LDO on
and off. When the SHDN pin is at a logic high
level, the LDO output is enabled. When the
SHDN pin is pulled to a logic low, the LDO output
is disabled. When disabled, the quiescent current
used by the LDO is less than 0.5 μA max.
3.4
Bypass
Connecting a low-value ceramic capacitor to the
Bypass pin will further reduce output voltage
noise and improve the PSRR performance of the
LDO. While smaller and larger values can be
used, these affect the speed at which the LDO
output voltage rises when the input power is
applied. The larger the bypass capacitor, the
slower the output voltage will rise.
3.5
Output Voltage (V
OUT
)
Connect the output load to V
OUT
of the LDO. Also
connect one side of the LDO output capacitor as
close as possible to the V
OUT
pin.
Pin No.
(5-Pin SOT-23)
Symbol
Description
1
V
IN
GND
Unregulated supply input.
2
Ground terminal.
3
SHDN
Shutdown control input. The regulator is fully enabled when a logic high is applied to
this input. The regulator enters shutdown when a logic low is applied to this input.
During shutdown, output voltage falls to zero and supply current is reduced to
0.5 μA (maximum).
4
Bypass
Reference bypass input. Connecting a 470 pF to this input further reduces output
noise.
5
V
OUT
Regulated voltage output.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TC1185-3.0VCT713 | 功能描述:低壓差穩(wěn)壓器 - LDO 150mA LDO w/Shtdn RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動(dòng)電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| TC1185-3.0VCT713-CUT TAPE | 制造商:Microchip 功能描述:TC1185 Series 150 mA 3.0 V CMOS LDO w/ Shutdown and VREF Bypass - SOT-23-5 |
| TC1185-3.3VCT713 | 功能描述:低壓差穩(wěn)壓器 - LDO 150mA LDO w/Shtdn RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動(dòng)電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| TC1185-3.3VCT713 | 制造商:Microchip Technology Inc 功能描述:V REG LDO +3.3V 1185 SOT-23A-5 |
| TC1185-3.6VCT713 | 功能描述:低壓差穩(wěn)壓器 - LDO 150mA LDO w/Shtdn RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動(dòng)電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20 |
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